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author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-08-20 19:11:10 +0200 |
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committer | tgingold <tgingold@users.noreply.github.com> | 2019-08-20 19:11:10 +0200 |
commit | 27ddfe66da98ad3ea058d29730454b19045d8621 (patch) | |
tree | df59c777410e1bcb87c1790cb19bc883c7e590a4 /src/synth/netlists-disp_vhdl.adb | |
parent | f64f2dbaa0e613f3ee499e6d474074d1b21c8bf4 (diff) | |
download | ghdl-27ddfe66da98ad3ea058d29730454b19045d8621.tar.gz ghdl-27ddfe66da98ad3ea058d29730454b19045d8621.tar.bz2 ghdl-27ddfe66da98ad3ea058d29730454b19045d8621.zip |
initial support for reduce and/or (#900)
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index d714f35fe..78676f5f0 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -707,6 +707,19 @@ package body Netlists.Disp_Vhdl is (" \o0 <= \i1; -- reduce or" & NL, Inst); end if; end; + when Id_Red_And => + declare + Iw : constant Width := Get_Width (Get_Input_Net (Inst, 0)); + begin + if Iw > 1 then + Disp_Template + (" \o0 <= '1' when \i0 = (\n0 downto 0 => '1') else '0';" + & NL, Inst, (0 => Iw - 1)); + else + Disp_Template + (" \o0 <= \i1; -- reduce or" & NL, Inst); + end if; + end; when Id_Assert => Disp_Template (" assert \i0 = '1' severity error;" & NL, Inst); when Id_Assume => |