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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-31 08:01:20 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-31 08:01:20 +0200 |
| commit | 59802f84a6be56ee145efd1422fd802c8729fc88 (patch) | |
| tree | 4e32791e98f74604e5b32fa82f64f463e4969734 /src/synth/netlists-disp_vhdl.adb | |
| parent | befcd7309285746fdb6c6af2424daf9329f682c1 (diff) | |
| download | ghdl-59802f84a6be56ee145efd1422fd802c8729fc88.tar.gz ghdl-59802f84a6be56ee145efd1422fd802c8729fc88.tar.bz2 ghdl-59802f84a6be56ee145efd1422fd802c8729fc88.zip | |
synth: remove insert gate.
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 0bbf480db..4d0780d3c 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -582,28 +582,6 @@ package body Netlists.Disp_Vhdl is end if; Put_Line (");"); end; - when Id_Insert => - declare - Iw : constant Width := Get_Width (Get_Input_Net (Inst, 1)); - Ow : constant Width := Get_Width (Get_Output (Inst, 0)); - Off : constant Uns32 := Get_Param_Uns32 (Inst, 0); - begin - Disp_Template (" \o0 <= ", Inst); - if Off + Iw + 1 = Ow then - Disp_Template ("\i0 (\n0) & ", Inst, (0 => Ow - 1)); - elsif Off + Iw < Ow then - Disp_Template ("\i0 (\n0 downto \n1) & ", Inst, - (0 => Ow - 1, 1 => Off + Iw)); - end if; - Disp_Template ("\i1", Inst); - if Off > 1 then - Disp_Template (" & \i0 (\n0 downto 0)", Inst, - (0 => Off - 1)); - elsif Off = 1 then - Disp_Template (" & \i0 (0)", Inst); - end if; - Disp_Template (";" & NL, Inst); - end; when Id_Dyn_Insert => declare -- I0: Input, I1: Value, I2: position |