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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-07 16:35:53 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-07 16:35:53 +0200 |
| commit | cb3468002497ab2090bef31d559e2eaf4747b90a (patch) | |
| tree | d4849b2d661408cd154ca98e7cb36c6aa95e7f5e /src/synth/netlists-disp_vhdl.adb | |
| parent | 1c29fa09e1f71e7fb389f451afab3bd2fb1264ab (diff) | |
| download | ghdl-cb3468002497ab2090bef31d559e2eaf4747b90a.tar.gz ghdl-cb3468002497ab2090bef31d559e2eaf4747b90a.tar.bz2 ghdl-cb3468002497ab2090bef31d559e2eaf4747b90a.zip | |
synth: add const_sb32, add smul/umul.
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index e131469d5..e97f3ff5a 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -645,7 +645,7 @@ package body Netlists.Disp_Vhdl is when Id_Sub => Disp_Template (" \o0 <= std_logic_vector (\ui0 - \ui1);" & NL, Inst); - when Id_Mul => + when Id_Umul => Disp_Template (" \o0 <= std_logic_vector (resize (\ui0 * \ui1, \n0));" & NL, Inst, (0 => Get_Width (Get_Output (Inst, 0)))); |