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author | Tristan Gingold <tgingold@free.fr> | 2019-07-10 18:57:37 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-10 19:06:06 +0200 |
commit | fef6c5f6fbec086f9b2a4bd73ccbcb346742ca0d (patch) | |
tree | df22da0ad581351798e1b09679464c2b29812b52 /src/synth/netlists-disp_vhdl.adb | |
parent | 52536adeb52c88676bbf4141fed7189ace6047c5 (diff) | |
download | ghdl-fef6c5f6fbec086f9b2a4bd73ccbcb346742ca0d.tar.gz ghdl-fef6c5f6fbec086f9b2a4bd73ccbcb346742ca0d.tar.bz2 ghdl-fef6c5f6fbec086f9b2a4bd73ccbcb346742ca0d.zip |
synth: display instances in reverse order.
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 33 |
1 files changed, 28 insertions, 5 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index d3ef8b728..72003c04f 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -708,11 +708,34 @@ package body Netlists.Disp_Vhdl is procedure Disp_Vhdl (M : Module; Is_Top : Boolean) is begin - for S of Sub_Modules (M) loop - if Get_Id (S) >= Id_User_None then - Disp_Vhdl (S, False); - end if; - end loop; + -- Disp in reverse order. + declare + Num : Natural; + begin + Num := 0; + for S of Sub_Modules (M) loop + if Get_Id (S) >= Id_User_None then + Num := Num + 1; + end if; + end loop; + + declare + type Module_Array is array (1 .. Num) of Module; + Modules : Module_Array; + begin + Num := 0; + for S of Sub_Modules (M) loop + if Get_Id (S) >= Id_User_None then + Num := Num + 1; + Modules (Num) := S; + end if; + end loop; + + for I in reverse Modules'Range loop + Disp_Vhdl (Modules (I), False); + end loop; + end; + end; if not Is_Top then Disp_Entity (M); |