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author | Tristan Gingold <tgingold@free.fr> | 2020-04-15 07:35:24 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-15 07:36:01 +0200 |
commit | 15539c0af43cc63d99239e3b65d936955cde3226 (patch) | |
tree | 97e95dcd9f260a3a7acf2cf48dde556416a65ecd /src/synth/netlists-gates.ads | |
parent | add25cf10b6886bfea9b2392e08142cee1698fd0 (diff) | |
download | ghdl-15539c0af43cc63d99239e3b65d936955cde3226.tar.gz ghdl-15539c0af43cc63d99239e3b65d936955cde3226.tar.bz2 ghdl-15539c0af43cc63d99239e3b65d936955cde3226.zip |
synth: rework edge handling to properly support falling edge. Fix #1227
Diffstat (limited to 'src/synth/netlists-gates.ads')
-rw-r--r-- | src/synth/netlists-gates.ads | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 04920b224..8dcb65cce 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -275,19 +275,20 @@ package Netlists.Gates is -- Virtual gate to gather 2 dffs of a multiport memory. Id_Mem_Multiport : constant Module_Id := 79; - -- Positive/rising edge detector. This is a pseudo gate. - -- A negative edge detector can be made using by negating the clock before - -- the detector. - Id_Edge : constant Module_Id := 80; + -- Positive/rising edge and negative/falling edge detector. + -- These are pseudo gates. + Id_Posedge : constant Module_Id := 80; + Id_Negedge : constant Module_Id := 81; + subtype Edge_Module_Id is Module_Id range Id_Posedge .. Id_Negedge; -- Input signal must always be true. - Id_Assert : constant Module_Id := 81; - Id_Assume : constant Module_Id := 82; + Id_Assert : constant Module_Id := 82; + Id_Assume : constant Module_Id := 83; -- Input is true when a sequence is covered. - Id_Cover : constant Module_Id := 83; + Id_Cover : constant Module_Id := 84; -- Use to cover the precedent of an assertion. - Id_Assert_Cover : constant Module_Id := 84; + Id_Assert_Cover : constant Module_Id := 85; -- Formal gates. Id_Allconst : constant Module_Id := 90; |