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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-17 02:18:01 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-17 02:18:01 +0200 |
| commit | b7a36d7d7838d05b449aa7e23935cd0e3e4213d4 (patch) | |
| tree | b50c865a4c0acfb5923e2402578417e5f6accd7c /src/synth/netlists-gates.ads | |
| parent | b3a28203e95f68bd1007c4c11b44187ecabbf593 (diff) | |
| download | ghdl-b7a36d7d7838d05b449aa7e23935cd0e3e4213d4.tar.gz ghdl-b7a36d7d7838d05b449aa7e23935cd0e3e4213d4.tar.bz2 ghdl-b7a36d7d7838d05b449aa7e23935cd0e3e4213d4.zip | |
synth-inference: detect false loop.
Diffstat (limited to 'src/synth/netlists-gates.ads')
| -rw-r--r-- | src/synth/netlists-gates.ads | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 124f933a4..b33da9778 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -86,6 +86,8 @@ package Netlists.Gates is -- Output: o Id_Mux4 : constant Module_Id := 37; + subtype Mux_Module_Id is Module_Id range Id_Mux2 .. Id_Mux4; + -- Like a wire: the output is equal to the input, but could be elimited -- at any time. Isignal has an initial value. Id_Signal : constant Module_Id := 38; |