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author | Tristan Gingold <tgingold@free.fr> | 2020-05-21 08:16:30 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-05-21 08:19:01 +0200 |
commit | 9576b788024d949f3324797c216a88f439d2df2e (patch) | |
tree | a00f864e2fa01482558df36872b367359f8f4fe2 /src/synth/netlists-inference.adb | |
parent | d32fa34618e1af8d47e8d462732685353ac7be27 (diff) | |
download | ghdl-9576b788024d949f3324797c216a88f439d2df2e.tar.gz ghdl-9576b788024d949f3324797c216a88f439d2df2e.tar.bz2 ghdl-9576b788024d949f3324797c216a88f439d2df2e.zip |
netlists-inference: Fix sequential assertions at init. Fix #1330
Diffstat (limited to 'src/synth/netlists-inference.adb')
-rw-r--r-- | src/synth/netlists-inference.adb | 29 |
1 files changed, 17 insertions, 12 deletions
diff --git a/src/synth/netlists-inference.adb b/src/synth/netlists-inference.adb index 574eed408..6263cbf62 100644 --- a/src/synth/netlists-inference.adb +++ b/src/synth/netlists-inference.adb @@ -928,12 +928,13 @@ package body Netlists.Inference is En_Gate : Net; Stmt : Synth.Source.Syn_Src) return Net is - Loc : constant Location_Type := Synth.Source."+" (Stmt); - Inst : Instance; - First_Inst, Last_Inst : Instance; - Clk, En : Net; - Areset : Net; - Zero : Net; + Loc : constant Location_Type := Synth.Source."+" (Stmt); + Inst : Instance; + First_Inst : Instance; + Last_Inst : Instance; + Clk, En : Net; + Areset : Net; + One : Net; begin -- Extract clock (if any) from VAL. Return VAL is no clock. First_Inst := Get_Net_Parent (Val); @@ -955,10 +956,13 @@ package body Netlists.Inference is Inst := Find_Condition_Chain_Next (Inst); end loop; + -- INST is the mux2 with clock CLK. + -- Extract enable and asynchronous reset (if any). Last_Inst := Inst; Areset := No_Net; - while Last_Inst /= Inst loop + Inst := First_Inst; + while Inst /= Last_Inst loop declare Cond : Net; Next_Inst : Instance; @@ -968,8 +972,8 @@ package body Netlists.Inference is -- Find the next mux. Next_Inst := Find_Condition_Chain_Next (Inst); - -- If the next mux is in0, negate COND. - if Next_Inst = Get_Net_Parent (Get_Input_Net (Inst, 1)) then + -- If the next mux is in1, negate COND. + if Next_Inst = Get_Net_Parent (Get_Input_Net (Inst, 2)) then Cond := Build_Monadic (Ctxt, Id_Not, Cond); Synth.Source.Set_Location (Cond, Stmt); end if; @@ -993,9 +997,10 @@ package body Netlists.Inference is end if; En := Build2_And (Ctxt, En, Get_Output (Next_Inst, 0), Loc); - Zero := Get_Input_Net (Inst, 1); end; + One := Build_Const_UB32 (Ctxt, 1, 1); + -- Build an idff/iadff for each condition of the assertions. -- The caller will connect the returned value (En) to the enable gate. declare @@ -1025,9 +1030,9 @@ package body Netlists.Inference is Disconnect (Assert_Inp); if Areset = No_Net then - Dff := Build_Idff (Ctxt, Clk, N, Zero); + Dff := Build_Idff (Ctxt, Clk, N, One); else - Dff := Build_Iadff (Ctxt, Clk, N, Areset, Zero, Zero); + Dff := Build_Iadff (Ctxt, Clk, N, Areset, One, One); end if; Set_Location (Dff, Loc); |