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author | Tristan Gingold <tgingold@free.fr> | 2021-11-28 18:14:34 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-11-28 18:14:34 +0100 |
commit | c7d32abe6f8108c0e7af6eea5d546be2bd83b704 (patch) | |
tree | 84a4983642cc21347c50a995605ab341b943b221 /src/synth/netlists-memories.adb | |
parent | 41600195196e67db0de2ea1e6b5ccbf792d97bfa (diff) | |
download | ghdl-c7d32abe6f8108c0e7af6eea5d546be2bd83b704.tar.gz ghdl-c7d32abe6f8108c0e7af6eea5d546be2bd83b704.tar.bz2 ghdl-c7d32abe6f8108c0e7af6eea5d546be2bd83b704.zip |
synth memories: also accept constant signal as memory initial value
Diffstat (limited to 'src/synth/netlists-memories.adb')
-rw-r--r-- | src/synth/netlists-memories.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/netlists-memories.adb b/src/synth/netlists-memories.adb index 9f89adaa0..062a73a94 100644 --- a/src/synth/netlists-memories.adb +++ b/src/synth/netlists-memories.adb @@ -2341,7 +2341,7 @@ package body Netlists.Memories is function Is_Const_Input (Inst : Instance) return Boolean is begin case Get_Id (Inst) is - when Id_Const_Bit => + when Constant_Module_Id => return True; when Id_Signal | Id_Isignal => |