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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-25 12:39:53 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-25 12:39:53 +0100 |
| commit | 60a469e6b5f3a6df29558e8e98fdc5510886dee3 (patch) | |
| tree | 15a0b0999c931b927006d97c9a19ec8dc00c19ef /src/synth/synth-decls.adb | |
| parent | 88430d7566d72714268f6be31e542600745a1036 (diff) | |
| download | ghdl-60a469e6b5f3a6df29558e8e98fdc5510886dee3.tar.gz ghdl-60a469e6b5f3a6df29558e8e98fdc5510886dee3.tar.bz2 ghdl-60a469e6b5f3a6df29558e8e98fdc5510886dee3.zip | |
synth: improve propagation of errors.
Diffstat (limited to 'src/synth/synth-decls.adb')
| -rw-r--r-- | src/synth/synth-decls.adb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 05e412f13..d61a67241 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -878,6 +878,8 @@ package body Synth.Decls is while Is_Valid (Decl) loop Synth_Declaration (Syn_Inst, Decl, Is_Subprg, Last_Type); + exit when Is_Error (Syn_Inst); + Decl := Get_Chain (Decl); end loop; end Synth_Declarations; @@ -892,6 +894,11 @@ package body Synth.Decls is Def_Val : Net; begin Val := Get_Value (Syn_Inst, Decl); + if Val = null then + pragma Assert (Is_Error (Syn_Inst)); + return; + end if; + Gate_Net := Get_Wire_Gate (Val.W); Gate := Get_Net_Parent (Gate_Net); case Get_Id (Gate) is |