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author | Tristan Gingold <tgingold@free.fr> | 2020-04-30 07:49:18 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-30 07:49:18 +0200 |
commit | d4db650b2aa78fc2712505bdf92c89fe1bd345b4 (patch) | |
tree | bff03a426e2e83df436339d2841927ff528c1455 /src/synth/synth-decls.adb | |
parent | 7c6d865f8c663917e943708a9032af297e17e0c7 (diff) | |
download | ghdl-d4db650b2aa78fc2712505bdf92c89fe1bd345b4.tar.gz ghdl-d4db650b2aa78fc2712505bdf92c89fe1bd345b4.tar.bz2 ghdl-d4db650b2aa78fc2712505bdf92c89fe1bd345b4.zip |
synth: also check default value of signals. For #1271
Diffstat (limited to 'src/synth/synth-decls.adb')
-rw-r--r-- | src/synth/synth-decls.adb | 44 |
1 files changed, 26 insertions, 18 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 9f10a6e61..2bf525559 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -789,6 +789,30 @@ package body Synth.Decls is end if; end Synth_Variable_Declaration; + procedure Synth_Signal_Declaration (Syn_Inst : Synth_Instance_Acc; + Decl : Node) + is + Def : constant Iir := Get_Default_Value (Decl); + -- Slot : constant Object_Slot_Type := Get_Info (Decl).Slot; + Init : Valtyp; + Obj_Typ : Type_Acc; + begin + Synth_Declaration_Type (Syn_Inst, Decl); + Create_Wire_Object (Syn_Inst, Wire_Signal, Decl); + if Is_Valid (Def) then + Obj_Typ := Get_Subtype_Object (Syn_Inst, Get_Type (Decl)); + Init := Synth_Expression_With_Type (Syn_Inst, Def, Obj_Typ); + Init := Synth_Subtype_Conversion (Init, Obj_Typ, False, Decl); + if not Is_Static (Init.Val) then + Error_Msg_Synth (+Decl, "signals cannot be used in default value " + & "of a signal"); + end if; + else + Init := No_Valtyp; + end if; + Create_Var_Wire (Syn_Inst, Decl, Init); + end Synth_Signal_Declaration; + procedure Synth_Object_Alias_Declaration (Syn_Inst : Synth_Instance_Acc; Decl : Node) is @@ -842,24 +866,8 @@ package body Synth.Decls is when Iir_Kind_Constant_Declaration => Synth_Constant_Declaration (Syn_Inst, Decl, Is_Subprg, Last_Type); when Iir_Kind_Signal_Declaration => - Synth_Declaration_Type (Syn_Inst, Decl); - declare - Def : constant Iir := Get_Default_Value (Decl); - -- Slot : constant Object_Slot_Type := Get_Info (Decl).Slot; - Init : Valtyp; - Obj_Typ : Type_Acc; - begin - Create_Wire_Object (Syn_Inst, Wire_Signal, Decl); - if Is_Valid (Def) then - Obj_Typ := Get_Subtype_Object (Syn_Inst, Get_Type (Decl)); - Init := Synth_Expression_With_Type (Syn_Inst, Def, Obj_Typ); - Init := Synth_Subtype_Conversion - (Init, Obj_Typ, False, Decl); - else - Init := No_Valtyp; - end if; - Create_Var_Wire (Syn_Inst, Decl, Init); - end; + pragma Assert (not Is_Subprg); + Synth_Signal_Declaration (Syn_Inst, Decl); when Iir_Kind_Object_Alias_Declaration => Synth_Object_Alias_Declaration (Syn_Inst, Decl); when Iir_Kind_Anonymous_Signal_Declaration => |