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author | Tristan Gingold <tgingold@free.fr> | 2020-03-22 19:36:44 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-22 19:36:44 +0100 |
commit | 0cd37c83c170b5292b5ec9800013da6b4f63c1c1 (patch) | |
tree | 3b8a1df5451df80e2da3d630eb8621dedbcd1d18 /src/synth/synth-disp_vhdl.adb | |
parent | 902d81ad69bb66a9515d09270c10d0f7ea167d25 (diff) | |
download | ghdl-0cd37c83c170b5292b5ec9800013da6b4f63c1c1.tar.gz ghdl-0cd37c83c170b5292b5ec9800013da6b4f63c1c1.tar.bz2 ghdl-0cd37c83c170b5292b5ec9800013da6b4f63c1c1.zip |
synth-disp_vhdl: do not wrap inout ports. For #1166
Diffstat (limited to 'src/synth/synth-disp_vhdl.adb')
-rw-r--r-- | src/synth/synth-disp_vhdl.adb | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index c5260bf5a..c60a65e59 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -44,13 +44,20 @@ package body Synth.Disp_Vhdl is Put_Line (";"); end Disp_Signal; - procedure Disp_Ports_As_Signals (M : Module) is + procedure Disp_Ports_As_Signals (M : Module) + is + Desc : Port_Desc; begin for I in 1 .. Get_Nbr_Inputs (M) loop Disp_Signal (Get_Input_Desc (M, I - 1)); end loop; for I in 1 .. Get_Nbr_Outputs (M) loop - Disp_Signal (Get_Output_Desc (M, I - 1)); + Desc := Get_Output_Desc (M, I - 1); + if not Desc.Is_Inout then + -- inout ports are not prefixed, so they must not be declared + -- as signals. + Disp_Signal (Desc); + end if; end loop; end Disp_Ports_As_Signals; @@ -439,7 +446,9 @@ package body Synth.Disp_Vhdl is Name_Wrap := Name_Table.Get_Identifier ("wrap"); for P of Ports_Desc (Main) loop pragma Assert (Get_Sname_Prefix (P.Name) = No_Sname); - Set_Sname_Prefix (P.Name, New_Sname_User (Name_Wrap, No_Sname)); + if not P.Is_Inout then + Set_Sname_Prefix (P.Name, New_Sname_User (Name_Wrap, No_Sname)); + end if; end loop; Put_Line ("library ieee;"); |