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| author | Tristan Gingold <tgingold@free.fr> | 2020-01-25 08:24:44 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-01-25 08:24:44 +0100 |
| commit | c2168c679ca3d634d7bdb7b1ca2fcb198d100b6d (patch) | |
| tree | 8ddd12121ebc3231d5c03b3e7b38675cd37db901 /src/synth/synth-disp_vhdl.adb | |
| parent | 383aa041762b77aea45c12d10c8d4178597b0fb8 (diff) | |
| download | ghdl-c2168c679ca3d634d7bdb7b1ca2fcb198d100b6d.tar.gz ghdl-c2168c679ca3d634d7bdb7b1ca2fcb198d100b6d.tar.bz2 ghdl-c2168c679ca3d634d7bdb7b1ca2fcb198d100b6d.zip | |
synth: improve support of 0-width nets and gates. Fix #1113
Diffstat (limited to 'src/synth/synth-disp_vhdl.adb')
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 43392147c..c5260bf5a 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -152,13 +152,19 @@ package body Synth.Disp_Vhdl is elsif Is_Std_Logic_Array (Btype) then W := Typ.Vbound.Len; Disp_In_Lhs (Mname, Off, W, Full); - Put ("std_logic_vector(" & Pfx); + if W > 1 then + Put ("std_logic_vector("); + end if; + Put (Pfx); if W = 1 then -- This is an array of length 1. A scalar is used in the -- netlist. Put (" (" & Pfx & "'left)"); end if; - Put_Line (");"); + if W > 1 then + Put (')'); + end if; + Put_Line (";"); elsif Btype = Vhdl.Std_Package.Bit_Vector_Type_Definition then W := Typ.Vbound.Len; Disp_In_Lhs (Mname, Off, W, Full); |