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authorTristan Gingold <tgingold@free.fr>2019-07-17 06:34:15 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-17 06:34:15 +0200
commit3ad0b11d266aa7d5c594f76722fb7fa67ec039de (patch)
tree746e1b4a09bff0a235c2665540363c8e0f9a87fb /src/synth/synth-environment.adb
parent3a1f9c3fa9ef0224c4add88cd6020d8a933426ee (diff)
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synth: make type Wire_Id_Record private.
Diffstat (limited to 'src/synth/synth-environment.adb')
-rw-r--r--src/synth/synth-environment.adb29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb
index 536ea5710..ce8bb6983 100644
--- a/src/synth/synth-environment.adb
+++ b/src/synth/synth-environment.adb
@@ -24,6 +24,35 @@ with Netlists.Builders; use Netlists.Builders;
with Synth.Inference;
package body Synth.Environment is
+ procedure Set_Wire_Mark (Wid : Wire_Id; Mark : Boolean := True) is
+ begin
+ Wire_Id_Table.Table (Wid).Mark_Flag := Mark;
+ end Set_Wire_Mark;
+
+ function Get_Wire_Mark (Wid : Wire_Id) return Boolean is
+ begin
+ return Wire_Id_Table.Table (Wid).Mark_Flag;
+ end Get_Wire_Mark;
+
+ function Alloc_Wire (Kind : Wire_Kind; Obj : Source.Syn_Src)
+ return Wire_Id is
+ begin
+ Wire_Id_Table.Append ((Kind => Kind,
+ Mark_Flag => False,
+ Decl => Obj,
+ Gate => No_Net,
+ Cur_Assign => No_Seq_Assign));
+ return Wire_Id_Table.Last;
+ end Alloc_Wire;
+
+ procedure Set_Wire_Gate (Wid : Wire_Id; Gate : Net) is
+ begin
+ -- Cannot override a gate.
+ pragma Assert (Wire_Id_Table.Table (Wid).Gate = No_Net);
+
+ Wire_Id_Table.Table (Wid).Gate := Gate;
+ end Set_Wire_Gate;
+
function Get_Wire_Id (W : Seq_Assign) return Wire_Id is
begin
return Assign_Table.Table (W).Id;