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author | Tristan Gingold <tgingold@free.fr> | 2019-09-11 06:31:00 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-11 06:37:28 +0200 |
commit | db5c3b1cf051d215ee7f02064464b4b1088ea226 (patch) | |
tree | e5aaacca93241b2ca61aa7572deb9bd722663ba0 /src/synth/synth-environment.adb | |
parent | 0e5e045b01b6425ae3551ad1c463d8f8f57907d7 (diff) | |
download | ghdl-db5c3b1cf051d215ee7f02064464b4b1088ea226.tar.gz ghdl-db5c3b1cf051d215ee7f02064464b4b1088ea226.tar.bz2 ghdl-db5c3b1cf051d215ee7f02064464b4b1088ea226.zip |
synth: improve support of return statement.
Diffstat (limited to 'src/synth/synth-environment.adb')
-rw-r--r-- | src/synth/synth-environment.adb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index 41e6140ac..5a517b7d5 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -61,6 +61,11 @@ package body Synth.Environment is Wire_Id_Table.Table (Wid).Gate := Gate; end Set_Wire_Gate; + function Get_Wire_Gate (Wid : Wire_Id) return Net is + begin + return Wire_Id_Table.Table (Wid).Gate; + end Get_Wire_Gate; + function Get_Wire_Id (W : Seq_Assign) return Wire_Id is begin return Assign_Table.Table (W).Id; |