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author | Tristan Gingold <tgingold@free.fr> | 2019-05-05 07:49:25 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:05:11 +0200 |
commit | 85d360929d13e6b0bcb082f144883a43f402ce22 (patch) | |
tree | f8d8135e12393588b7704318f26304dfab272658 /src/synth/synth-expr.adb | |
parent | 3c48cc2a70085eef63718e622b3d1a7b75a2f36f (diff) | |
download | ghdl-85d360929d13e6b0bcb082f144883a43f402ce22.tar.gz ghdl-85d360929d13e6b0bcb082f144883a43f402ce22.tar.bz2 ghdl-85d360929d13e6b0bcb082f144883a43f402ce22.zip |
vhdl: move std_standard package to vhdl child.
Diffstat (limited to 'src/synth/synth-expr.adb')
-rw-r--r-- | src/synth/synth-expr.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index dea474e6c..cbc9f87d2 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -22,7 +22,7 @@ with Ada.Unchecked_Conversion; with Ada.Unchecked_Deallocation; with Std_Names; with Ieee.Std_Logic_1164; -with Std_Package; +with Vhdl.Std_Package; with Errorout; use Errorout; with Simul.Execution; with Grt.Types; use Grt.Types; @@ -695,11 +695,11 @@ package body Synth.Expr is return Build_Edge (Build_Context, True, Clk); end if; Lit := Get_Named_Entity (Right); - if Lit = Std_Package.Bit_0 + if Lit = Vhdl.Std_Package.Bit_0 or else Lit = Ieee.Std_Logic_1164.Std_Ulogic_0 then Posedge := False; - elsif Lit = Std_Package.Bit_1 + elsif Lit = Vhdl.Std_Package.Bit_1 or else Lit = Ieee.Std_Logic_1164.Std_Ulogic_1 then Posedge := True; |