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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-08-15 09:59:45 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-08-15 09:59:45 +0200 |
| commit | f7f0f0a48f49e0328401c1f60575f07c92c0c15f (patch) | |
| tree | faf86e849be57a31d082fb322b65a5270c7e772f /src/synth/synth-expr.adb | |
| parent | 473e61a9f37534d08aab4dc26c5eada258637974 (diff) | |
| download | ghdl-f7f0f0a48f49e0328401c1f60575f07c92c0c15f.tar.gz ghdl-f7f0f0a48f49e0328401c1f60575f07c92c0c15f.tar.bz2 ghdl-f7f0f0a48f49e0328401c1f60575f07c92c0c15f.zip | |
add synthesis support for logic operators on numeric types (#893)
* add logic operators on unsigned
* handle signed too
* handle unary not
Diffstat (limited to 'src/synth/synth-expr.adb')
| -rw-r--r-- | src/synth/synth-expr.adb | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 592f25297..43a2f4c3b 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -933,12 +933,30 @@ package body Synth.Expr is | Iir_Predefined_Ieee_1164_Scalar_Xnor => return Synth_Bit_Dyadic (Id_Xnor); - when Iir_Predefined_Ieee_1164_Vector_And => + when Iir_Predefined_Ieee_1164_Vector_And + | Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn => return Synth_Vec_Dyadic (Id_And); - when Iir_Predefined_Ieee_1164_Vector_Or => + when Iir_Predefined_Ieee_1164_Vector_Or + | Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn => return Synth_Vec_Dyadic (Id_Or); - when Iir_Predefined_Ieee_1164_Vector_Xor => + when Iir_Predefined_Ieee_1164_Vector_Nand + | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Sgn => + return Synth_Vec_Dyadic (Id_Nand); + when Iir_Predefined_Ieee_1164_Vector_Nor + | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Sgn => + return Synth_Vec_Dyadic (Id_Nor); + when Iir_Predefined_Ieee_1164_Vector_Xor + | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn => return Synth_Vec_Dyadic (Id_Xor); + when Iir_Predefined_Ieee_1164_Vector_Xnor + | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn => + return Synth_Vec_Dyadic (Id_Xnor); when Iir_Predefined_Enum_Equality => if Is_Bit_Type (Left_Type) then @@ -1218,7 +1236,9 @@ package body Synth.Expr is return null; when Iir_Predefined_Ieee_1164_Scalar_Not => return Synth_Bit_Monadic (Id_Not); - when Iir_Predefined_Ieee_1164_Vector_Not => + when Iir_Predefined_Ieee_1164_Vector_Not + | Iir_Predefined_Ieee_Numeric_Std_Not_Uns + | Iir_Predefined_Ieee_Numeric_Std_Not_Sgn => return Synth_Vec_Monadic (Id_Not); when Iir_Predefined_Ieee_Numeric_Std_Neg_Uns | Iir_Predefined_Ieee_Numeric_Std_Neg_Sgn => |