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authorTristan Gingold <tgingold@free.fr>2020-09-20 08:43:25 +0200
committerTristan Gingold <tgingold@free.fr>2020-09-20 08:43:25 +0200
commit76a3614439971b635828b004c6041f3ffbceb83d (patch)
tree6c91b39b04cf046b0c9ef91e6a5f58b3b32e359a /src/synth/synth-ieee-numeric_std.adb
parent1337962c251723acaf021a8df2efbc261804f88a (diff)
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synth: handle static resize. For #1460
Diffstat (limited to 'src/synth/synth-ieee-numeric_std.adb')
-rw-r--r--src/synth/synth-ieee-numeric_std.adb29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/synth/synth-ieee-numeric_std.adb b/src/synth/synth-ieee-numeric_std.adb
index 47e2e2a54..2c0951f3b 100644
--- a/src/synth/synth-ieee-numeric_std.adb
+++ b/src/synth/synth-ieee-numeric_std.adb
@@ -854,6 +854,35 @@ package body Synth.Ieee.Numeric_Std is
return Res;
end Shift_Vec;
+ function Resize_Vec (Val : Memtyp;
+ Size : Uns32;
+ Signed : Boolean) return Memtyp
+ is
+ Old_Size : constant Uns32 := Uns32 (Vec_Length (Val.Typ));
+ Res : Memtyp;
+ Pad, B : Std_Ulogic;
+ begin
+ Res.Typ := Create_Res_Type (Val.Typ, Size);
+ Res := Create_Memory (Res.Typ);
+
+ if Signed and then Old_Size > 0 then
+ Pad := Read_Std_Logic (Val.Mem, 0);
+ else
+ Pad := '0';
+ end if;
+
+ for I in 1 .. Size loop
+ if I <= Old_Size then
+ B := Read_Std_Logic (Val.Mem, I - 1);
+ else
+ B := Pad;
+ end if;
+ Write_Std_Logic (Res.Mem, I - 1, B);
+ end loop;
+
+ return Res;
+ end Resize_Vec;
+
type Std_Logic_Vector_Type is array (Uns32 range <>) of Std_Ulogic;
procedure Divmod (Num, Dem : Memtyp; Quot, Remain : Memtyp)