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authorTristan Gingold <tgingold@free.fr>2020-03-13 05:40:07 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-13 06:30:35 +0100
commit32e785f4108e1b4afd9a4aa20b908fb5c11cb737 (patch)
treeb84a2fe34a0d9fabbd47d4368945a1b733b6f7a8 /src/synth/synth-ieee-std_logic_1164.ads
parent0c130072578b486ad74e19e96571c500138f81dc (diff)
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synth-static_oper: handle unsigned "<".
Diffstat (limited to 'src/synth/synth-ieee-std_logic_1164.ads')
-rw-r--r--src/synth/synth-ieee-std_logic_1164.ads6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/synth/synth-ieee-std_logic_1164.ads b/src/synth/synth-ieee-std_logic_1164.ads
index 433825e86..a328f6dec 100644
--- a/src/synth/synth-ieee-std_logic_1164.ads
+++ b/src/synth/synth-ieee-std_logic_1164.ads
@@ -35,12 +35,18 @@ package Synth.Ieee.Std_Logic_1164 is
'-' -- Don't care.
);
+ subtype X01 is Std_Ulogic range 'X' .. '1';
+
-- Vector of logic state.
type Std_Logic_Vector is array (Natural range <>) of Std_Ulogic;
type Table_1d is array (Std_Ulogic) of Std_Ulogic;
type Table_2d is array (Std_Ulogic, Std_Ulogic) of Std_Ulogic;
+ type Table_1d_X01 is array (Std_Ulogic) of X01;
+
+ To_X01 : constant Table_1d_X01 := "XX01XX01X";
+
And_Table : constant Table_2d :=
-- UX01ZWLH-
("UU0UUU0UU", -- U