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| author | Tristan Gingold <tgingold@free.fr> | 2020-02-10 18:21:38 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-02-10 18:21:38 +0100 |
| commit | 7957698f300c2ad7ee33c4d43ad80ba3ecfe8253 (patch) | |
| tree | 04dbd02f0bc2f44b4dca21d99ba57ca1e505b17f /src/synth/synth-insts.adb | |
| parent | 2263b763e2dbd7ca624e66d15885ac1a664f886c (diff) | |
| download | ghdl-7957698f300c2ad7ee33c4d43ad80ba3ecfe8253.tar.gz ghdl-7957698f300c2ad7ee33c4d43ad80ba3ecfe8253.tar.bz2 ghdl-7957698f300c2ad7ee33c4d43ad80ba3ecfe8253.zip | |
synth: remove remaining clock edge gates after memories.
Diffstat (limited to 'src/synth/synth-insts.adb')
| -rw-r--r-- | src/synth/synth-insts.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index 9e15e04cc..4c9f72fd0 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -1412,6 +1412,8 @@ package body Synth.Insts is if not Synth.Flags.Flag_Debug_Nomemory then Netlists.Memories.Extract_Memories2 (Get_Build (Syn_Inst), Inst.M); + -- Remove remaining clock edge gates. + Netlists.Cleanup.Mark_And_Sweep (Inst.M); end if; if not Synth.Flags.Flag_Debug_Noexpand then |