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| author | Tristan Gingold <tgingold@free.fr> | 2020-08-26 18:18:17 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-08-26 22:39:02 +0200 |
| commit | d7f0f4d54961c65fbf5b98eb97d125c23de534f6 (patch) | |
| tree | b3dc6a3d2896c10855a86566cf2673e4e2a0adda /src/synth/synth-insts.adb | |
| parent | 11b90ee7beec457e4ee905837beb1041fee6c375 (diff) | |
| download | ghdl-d7f0f4d54961c65fbf5b98eb97d125c23de534f6.tar.gz ghdl-d7f0f4d54961c65fbf5b98eb97d125c23de534f6.tar.bz2 ghdl-d7f0f4d54961c65fbf5b98eb97d125c23de534f6.zip | |
synth: improve diagnostic for multiple assignment. Fix #1428
Diffstat (limited to 'src/synth/synth-insts.adb')
| -rw-r--r-- | src/synth/synth-insts.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index 93b8a510e..fe02de317 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -1012,7 +1012,7 @@ package body Synth.Insts is case Val.Val.Kind is when Value_Wire => -- Create a gate for the output, so that it could be read. - Val.Val.W := Alloc_Wire (Wire_Output, Inter); + Val.Val.W := Alloc_Wire (Wire_Output, Bit_Type, Inter); W := Get_Type_Width (Val.Typ); Value := Build_Signal (Ctxt, New_Internal_Name (Ctxt, Pfx_Name), W); @@ -1339,7 +1339,7 @@ package body Synth.Insts is pragma Assert (Val.Val.Kind = Value_Wire); -- Create a gate for the output, so that it could be read. - Val.Val.W := Alloc_Wire (Wire_Output, Inter); + Val.Val.W := Alloc_Wire (Wire_Output, Val.Typ, Inter); -- pragma Assert (Desc.W = Get_Type_Width (Val.Typ)); Inp := Get_Input (Self_Inst, Idx); |