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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-21 14:23:20 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-21 14:23:20 +0200 |
| commit | 182b9ba62518fb252e0cf6ad0381f33c88f7407a (patch) | |
| tree | 13e396ab1538cbbba1375b9f0f8b9e6a919d3081 /src/synth/synth-oper.adb | |
| parent | 129c89c888ac617e875d012676c00782c2b1e8d4 (diff) | |
| download | ghdl-182b9ba62518fb252e0cf6ad0381f33c88f7407a.tar.gz ghdl-182b9ba62518fb252e0cf6ad0381f33c88f7407a.tar.bz2 ghdl-182b9ba62518fb252e0cf6ad0381f33c88f7407a.zip | |
synth: handle more operators from std_logic_arith. Fix synth121
Diffstat (limited to 'src/synth/synth-oper.adb')
| -rw-r--r-- | src/synth/synth-oper.adb | 32 |
1 files changed, 19 insertions, 13 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 22e455b55..9ab0fd6ee 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -906,32 +906,34 @@ package body Synth.Oper is return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Ctxt, Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log - | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns - | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns => + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns => -- "-" (Unsigned, Unsigned) return Synth_Dyadic_Uns_Uns (Ctxt, Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns => -- "-" (Natural, Unsigned) return Synth_Dyadic_Nat_Uns (Ctxt, Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int - | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int => + | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int => -- "-" (Signed, Integer) return Synth_Dyadic_Sgn_Int (Ctxt, Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn => -- "-" (Integer, Signed) return Synth_Dyadic_Int_Sgn (Ctxt, Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn - | Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log - | Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn - | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv => + | Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log + | Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn + | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv => -- "-" (Signed, Signed) return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Sub, Left, Right, Expr); @@ -1591,6 +1593,7 @@ package body Synth.Oper is return Create_Value_Net (Get_Net (Ctxt, L), Create_Res_Bound (L)); when Iir_Predefined_Ieee_1164_To_Bit => return Create_Value_Net (Get_Net (Ctxt, L), Res_Typ); + when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int => return Synth_Conv_Vector (False); @@ -1605,10 +1608,12 @@ package body Synth.Oper is return Create_Value_Net (Synth_Uresize (Ctxt, Get_Net (Ctxt, L), Res_Typ.W, Expr), Res_Typ); - when Iir_Predefined_Ieee_Numeric_Std_Toint_Sgn_Int => + when Iir_Predefined_Ieee_Numeric_Std_Toint_Sgn_Int + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn => -- SIGNED to Integer. return Create_Value_Net (Synth_Sresize (Ctxt, L, Res_Typ.W, Expr), Res_Typ); + when Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Nat | Iir_Predefined_Ieee_Std_Logic_Arith_Ext => declare @@ -1624,7 +1629,8 @@ package body Synth.Oper is Create_Vec_Type_By_Length (W, Logic_Type)); end; when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat - | Iir_Predefined_Ieee_Std_Logic_Arith_Sxt => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Sxt => declare W : Width; begin |