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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:21:24 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:21:24 +0200 |
| commit | 2714a30c3753c76cda95eb994851a8be95e60ad9 (patch) | |
| tree | ed759d92892d21a21cc5e60e2995e9feef5ed1a2 /src/synth/synth-oper.adb | |
| parent | f4be996776af67b5242e9ec5fc18ec1fe27d0efb (diff) | |
| download | ghdl-2714a30c3753c76cda95eb994851a8be95e60ad9.tar.gz ghdl-2714a30c3753c76cda95eb994851a8be95e60ad9.tar.bz2 ghdl-2714a30c3753c76cda95eb994851a8be95e60ad9.zip | |
vhdl: recognize minus from std_logic_unsigned
Diffstat (limited to 'src/synth/synth-oper.adb')
| -rw-r--r-- | src/synth/synth-oper.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index bdea830f1..62bc1a51e 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -507,7 +507,8 @@ package body Synth.Oper is -- "+" (Signed, Signed) return Synth_Dyadic_Sgn (Id_Add, True); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Id_Sub); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns => |