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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-03 19:55:23 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-03 19:55:23 +0200 |
| commit | 8f711316e523cb8fb8cb994345793ab8951f9987 (patch) | |
| tree | ba2d71e1c9e5327440f6788fac0af98dc82f55fa /src/synth/synth-oper.adb | |
| parent | 86a93728739ef1dc261856be3935321185736fe9 (diff) | |
| download | ghdl-8f711316e523cb8fb8cb994345793ab8951f9987.tar.gz ghdl-8f711316e523cb8fb8cb994345793ab8951f9987.tar.bz2 ghdl-8f711316e523cb8fb8cb994345793ab8951f9987.zip | |
synth: remove unused wlen field of bound_type.
Diffstat (limited to 'src/synth/synth-oper.adb')
| -rw-r--r-- | src/synth/synth-oper.adb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 13afb0ea8..92508f36d 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -21,7 +21,6 @@ with Ada.Unchecked_Conversion; with Types; use Types; with Types_Utils; use Types_Utils; -with Mutils; use Mutils; with Vhdl.Ieee.Std_Logic_1164; use Vhdl.Ieee.Std_Logic_1164; with Vhdl.Std_Package; with Vhdl.Errors; use Vhdl.Errors; @@ -160,7 +159,6 @@ package body Synth.Oper is Right => 0, Dir => Index_Bounds.Dir, Wbounds => W, - Wlen => Width (Clog2 (Uns64 (Len))), Len => Uns32 (Len)); if Len = 0 then |