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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-27 08:00:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-27 08:00:42 +0200 |
| commit | 67f926fc1323c375d14fee36a092e39a92d505dd (patch) | |
| tree | 2721ed6d11218bd9db3358e913d08f874dc9bc6a /src/synth/synth-static_oper.adb | |
| parent | defe3b033f1c3026312c94e5ce661172c670e9a5 (diff) | |
| download | ghdl-67f926fc1323c375d14fee36a092e39a92d505dd.tar.gz ghdl-67f926fc1323c375d14fee36a092e39a92d505dd.tar.bz2 ghdl-67f926fc1323c375d14fee36a092e39a92d505dd.zip | |
synth: handle reduction operators. Fix #1342
Diffstat (limited to 'src/synth/synth-static_oper.adb')
| -rw-r--r-- | src/synth/synth-static_oper.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index ade651703..8b72dc3e7 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -697,7 +697,7 @@ package body Synth.Static_Oper is (Std_Ulogic'Pos (Not_Table (Read_Std_Logic (Operand.Mem, 0))), Oper_Typ); - when Iir_Predefined_Ieee_1164_Vector_Or_Reduce => + when Iir_Predefined_Ieee_1164_Or_Suv => return Synth_Vector_Reduce ('0', Operand, Or_Table); when others => |