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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-17 06:34:15 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-17 06:34:15 +0200 |
| commit | 3ad0b11d266aa7d5c594f76722fb7fa67ec039de (patch) | |
| tree | 746e1b4a09bff0a235c2665540363c8e0f9a87fb /src/synth/synth-stmts.adb | |
| parent | 3a1f9c3fa9ef0224c4add88cd6020d8a933426ee (diff) | |
| download | ghdl-3ad0b11d266aa7d5c594f76722fb7fa67ec039de.tar.gz ghdl-3ad0b11d266aa7d5c594f76722fb7fa67ec039de.tar.bz2 ghdl-3ad0b11d266aa7d5c594f76722fb7fa67ec039de.zip | |
synth: make type Wire_Id_Record private.
Diffstat (limited to 'src/synth/synth-stmts.adb')
| -rw-r--r-- | src/synth/synth-stmts.adb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 6fb9e9313..1f37f25bc 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -418,9 +418,9 @@ package body Synth.Stmts is Asgn := Alts (I).Asgns; while Asgn /= No_Seq_Assign loop W := Get_Wire_Id (Asgn); - if not Wire_Id_Table.Table (W).Mark_Flag then + if not Get_Wire_Mark (W) then Res := Res + 1; - Wire_Id_Table.Table (W).Mark_Flag := True; + Set_Wire_Mark (W, True); end if; Asgn := Get_Assign_Chain (Asgn); end loop; @@ -440,10 +440,10 @@ package body Synth.Stmts is Asgn := Alts (I).Asgns; while Asgn /= No_Seq_Assign loop W := Get_Wire_Id (Asgn); - if Wire_Id_Table.Table (W).Mark_Flag then + if Get_Wire_Mark (W) then Arr (Idx) := W; Idx := Idx + 1; - Wire_Id_Table.Table (W).Mark_Flag := False; + Set_Wire_Mark (W, False); end if; Asgn := Get_Assign_Chain (Asgn); end loop; |