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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:22:30 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:22:30 +0200 |
| commit | d6cda1098e82a15bb905235c46992cd7de9bb690 (patch) | |
| tree | db6e15e289fa144304176623b4ff4cb96915e661 /src/synth/synth-stmts.adb | |
| parent | 457ab6ebd8b17685c79047ad6d50e1b26665c5c3 (diff) | |
| download | ghdl-d6cda1098e82a15bb905235c46992cd7de9bb690.tar.gz ghdl-d6cda1098e82a15bb905235c46992cd7de9bb690.tar.bz2 ghdl-d6cda1098e82a15bb905235c46992cd7de9bb690.zip | |
synth: use future states for PSL restrict directive.
Diffstat (limited to 'src/synth/synth-stmts.adb')
| -rw-r--r-- | src/synth/synth-stmts.adb | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 9ed350e4d..cd60d4ff0 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1154,7 +1154,7 @@ package body Synth.Stmts is Init : Net; Clk : Net; States : Net; - Res : Net; + Next_States : Net; begin -- create init net, clock net pragma Assert (Nbr_States <= 32); @@ -1166,13 +1166,16 @@ package body Synth.Stmts is -- create update nets -- For each state: if set, evaluate all outgoing edges. - Res := Synth_Psl_NFA (Syn_Inst, Get_PSL_NFA (Stmt), Nbr_States, States); - Connect (Get_Input (Get_Parent (States), 1), Res); + Next_States := + Synth_Psl_NFA (Syn_Inst, Get_PSL_NFA (Stmt), Nbr_States, States); + Connect (Get_Input (Get_Parent (States), 1), Next_States); - -- build assume gate + -- Build assume gate. + -- Note: for synthesis, we assume the next state will be correct. + -- (If we assume on States, then the first cycle is ignored). Build_Assume (Build_Context, Build_Reduce (Build_Context, - Netlists.Gates.Id_Red_Or, States)); + Netlists.Gates.Id_Red_Or, Next_States)); end Synth_Psl_Restrict_Directive; procedure Synth_Concurrent_Statements |