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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-16 08:31:03 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-16 08:31:03 +0200 |
| commit | ae7667c05858b9d7f6c1637a06497dfa138f635e (patch) | |
| tree | f44915b0e2147190f5123056febe0ff429fbe347 /src/synth/synth-vhdl_context.adb | |
| parent | 37d38f613b065b59b6d13aabaad3295861504296 (diff) | |
| download | ghdl-ae7667c05858b9d7f6c1637a06497dfa138f635e.tar.gz ghdl-ae7667c05858b9d7f6c1637a06497dfa138f635e.tar.bz2 ghdl-ae7667c05858b9d7f6c1637a06497dfa138f635e.zip | |
elab-vhdl_values: add Create_Value_Quantity
Diffstat (limited to 'src/synth/synth-vhdl_context.adb')
| -rw-r--r-- | src/synth/synth-vhdl_context.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index f9c1edb39..6e498afdf 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -448,6 +448,8 @@ package body Synth.Vhdl_Context is | Value_Signal | Value_Dyn_Alias => return False; + when Value_Quantity => + return False; when Value_Wire => declare W : constant Wire_Id := Get_Value_Wire (Val); |