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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-05 09:48:25 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-05 09:48:25 +0200 |
| commit | a04e3a9b0451a9564e0cdafae22dd471b463559e (patch) | |
| tree | ca14b11e84c05f0d93a36183b53919cc3c61e2e5 /src/synth/synth-vhdl_eval.adb | |
| parent | 9a001446dd281c47a8321ce475bcf1e79dc1b859 (diff) | |
| download | ghdl-a04e3a9b0451a9564e0cdafae22dd471b463559e.tar.gz ghdl-a04e3a9b0451a9564e0cdafae22dd471b463559e.tar.bz2 ghdl-a04e3a9b0451a9564e0cdafae22dd471b463559e.zip | |
synth-vhdl_eval: handle more operations
Diffstat (limited to 'src/synth/synth-vhdl_eval.adb')
| -rw-r--r-- | src/synth/synth-vhdl_eval.adb | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index f69fe6192..36e0c6c03 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -1080,12 +1080,17 @@ package body Synth.Vhdl_Eval is end; when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns - | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv => return Add_Uns_Uns (Left, Right, +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log => + return Add_Uns_Uns (Left, Log_To_Vec (Right, Left), +Expr); + + when Iir_Predefined_Ieee_Numeric_Std_Add_Log_Uns => + return Add_Uns_Uns (Log_To_Vec (Left, Right), Right, +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int => return Add_Uns_Nat (Left, To_Uns64 (Read_Discrete (Right)), +Expr); @@ -1099,6 +1104,11 @@ package body Synth.Vhdl_Eval is when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn => return Add_Sgn_Int (Right, Read_Discrete (Left), +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log => + return Add_Sgn_Sgn (Left, Log_To_Vec (Right, Left), +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn => + return Add_Sgn_Sgn (Log_To_Vec (Left, Right), Right, +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns => return Sub_Uns_Uns (Left, Right, +Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat => @@ -1106,6 +1116,11 @@ package body Synth.Vhdl_Eval is when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns => return Sub_Nat_Uns (To_Uns64 (Read_Discrete (Left)), Right, +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Log => + return Sub_Uns_Uns (Left, Log_To_Vec (Right, Left), +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Uns => + return Sub_Uns_Uns (Log_To_Vec (Left, Right), Right, +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn => return Sub_Sgn_Sgn (Left, Right, +Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int => @@ -1113,6 +1128,11 @@ package body Synth.Vhdl_Eval is when Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn => return Sub_Int_Sgn (Read_Discrete (Left), Right, +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log => + return Sub_Sgn_Sgn (Left, Log_To_Vec (Right, Left), +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn => + return Sub_Sgn_Sgn (Log_To_Vec (Left, Right), Right, +Expr); + when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns => return Mul_Uns_Uns (Left, Right, +Expr); when Iir_Predefined_Ieee_Numeric_Std_Mul_Nat_Uns => |