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| author | Tristan Gingold <tgingold@free.fr> | 2023-02-09 07:53:57 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-02-09 07:53:57 +0100 |
| commit | d1ff79789a621a485aeb4c854ce136c9f6a8ff70 (patch) | |
| tree | 23a7ce595c0b7e3e025583ed8dcadd9e91f669cc /src/synth/synth-vhdl_eval.adb | |
| parent | 7a0759479a991ab9ec1e2716f34b738a0286fa9a (diff) | |
| download | ghdl-d1ff79789a621a485aeb4c854ce136c9f6a8ff70.tar.gz ghdl-d1ff79789a621a485aeb4c854ce136c9f6a8ff70.tar.bz2 ghdl-d1ff79789a621a485aeb4c854ce136c9f6a8ff70.zip | |
synth-vhdl_eval: handle std_logic_arith.conv_std_logic_vector
Fix #2347
Diffstat (limited to 'src/synth/synth-vhdl_eval.adb')
| -rw-r--r-- | src/synth/synth-vhdl_eval.adb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 2cc70bd52..020c67896 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -2710,6 +2710,13 @@ package body Synth.Vhdl_Eval is return Resize_Vec (Param1, Uns32 (Len), True); end; + when Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn => + return Conv_Slv + (Param1, Uns32 (Read_Discrete (Param2)), True, +Expr); + when Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Uns => + return Conv_Slv + (Param1, Uns32 (Read_Discrete (Param2)), False, +Expr); + when Iir_Predefined_Ieee_1164_To_Stdulogic => declare B : Std_Ulogic; |