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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-31 08:16:39 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-31 18:28:27 +0200 |
| commit | ed34178a6e1e7cef8df938c10480452709698934 (patch) | |
| tree | fb8d3dcc4c57a27c98bc782c575b36572481bccf /src/synth/synth-vhdl_eval.adb | |
| parent | 86ef00fb705b4508a5fec4bd014d304502401960 (diff) | |
| download | ghdl-ed34178a6e1e7cef8df938c10480452709698934.tar.gz ghdl-ed34178a6e1e7cef8df938c10480452709698934.tar.bz2 ghdl-ed34178a6e1e7cef8df938c10480452709698934.zip | |
synth-vhdl_eval: complete vector reduce operations
Diffstat (limited to 'src/synth/synth-vhdl_eval.adb')
| -rw-r--r-- | src/synth/synth-vhdl_eval.adb | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 115c1b4b9..4a45fb989 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -1089,8 +1089,10 @@ package body Synth.Vhdl_Eval is return Res; end Eval_Vector_Monadic; - function Eval_Vector_Reduce - (Init : Std_Ulogic; Vec : Memtyp; Op : Table_2d) return Memtyp + function Eval_Vector_Reduce (Init : Std_Ulogic; + Vec : Memtyp; + Op : Table_2d; + Neg : Boolean) return Memtyp is El_Typ : constant Type_Acc := Vec.Typ.Arr_El; Res : Std_Ulogic; @@ -1104,6 +1106,10 @@ package body Synth.Vhdl_Eval is end; end loop; + if Neg then + Res := Not_Table (Res); + end if; + return Create_Memory_U8 (Std_Ulogic'Pos (Res), El_Typ); end Eval_Vector_Reduce; @@ -1335,14 +1341,22 @@ package body Synth.Vhdl_Eval is (Std_Ulogic'Pos (Not_Table (Read_Std_Logic (Operand.Mem, 0))), Operand.Typ); - when Iir_Predefined_Ieee_Numeric_Std_And_Uns => - return Eval_Vector_Reduce ('1', Operand, And_Table); + when Iir_Predefined_Ieee_1164_And_Suv + | Iir_Predefined_Ieee_Numeric_Std_And_Uns => + return Eval_Vector_Reduce ('1', Operand, And_Table, False); + when Iir_Predefined_Ieee_1164_Nand_Suv => + return Eval_Vector_Reduce ('1', Operand, And_Table, True); when Iir_Predefined_Ieee_1164_Or_Suv - | Iir_Predefined_Ieee_Numeric_Std_Or_Uns => - return Eval_Vector_Reduce ('0', Operand, Or_Table); + | Iir_Predefined_Ieee_Numeric_Std_Or_Uns => + return Eval_Vector_Reduce ('0', Operand, Or_Table, False); + when Iir_Predefined_Ieee_1164_Nor_Suv => + return Eval_Vector_Reduce ('0', Operand, Or_Table, True); + when Iir_Predefined_Ieee_1164_Xor_Suv => - return Eval_Vector_Reduce ('0', Operand, Xor_Table); + return Eval_Vector_Reduce ('0', Operand, Xor_Table, False); + when Iir_Predefined_Ieee_1164_Xnor_Suv => + return Eval_Vector_Reduce ('0', Operand, Xor_Table, True); when others => Error_Msg_Synth |