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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-29 08:44:22 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-29 08:44:22 +0200 |
| commit | 91f74c1d54b9e5547e38fbbacb0f25fe3b22be3a (patch) | |
| tree | 6ee69a85d684d2177259dc2464e33b913094821f /src/synth/synth-vhdl_expr.adb | |
| parent | 4542748c790c6e2b2606e6dbfe64bd0468c292b4 (diff) | |
| download | ghdl-91f74c1d54b9e5547e38fbbacb0f25fe3b22be3a.tar.gz ghdl-91f74c1d54b9e5547e38fbbacb0f25fe3b22be3a.tar.bz2 ghdl-91f74c1d54b9e5547e38fbbacb0f25fe3b22be3a.zip | |
synth-vhdl_oper: add hook for falling edge, handle aliases.
Diffstat (limited to 'src/synth/synth-vhdl_expr.adb')
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 6ec6e5e12..eee24353f 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -1867,8 +1867,10 @@ package body Synth.Vhdl_Expr is Get_Implicit_Definition (Imp); Edge : Net; begin - -- Match clock-edge - if Def = Iir_Predefined_Boolean_And then + -- Match clock-edge (only for synthesis) + if Def = Iir_Predefined_Boolean_And + and then Hook_Signal_Expr = null + then Edge := Synth_Clock_Edge (Syn_Inst, Get_Left (Expr), Get_Right (Expr)); if Edge /= No_Net then @@ -1938,7 +1940,10 @@ package body Synth.Vhdl_Expr is begin Res := Synth_Name (Syn_Inst, Expr); if Res.Val /= null - and then Res.Val.Kind = Value_Signal + and then + (Res.Val.Kind = Value_Signal + or else (Res.Val.Kind = Value_Alias + and then Res.Val.A_Obj.Kind = Value_Signal)) then if Hook_Signal_Expr /= null then return Hook_Signal_Expr (Res); |