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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-06 08:07:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-06 08:07:09 +0200 |
| commit | 3929ff5f232481b965ab4da4503fc515d577e4c5 (patch) | |
| tree | 5b192069f9dabf0ed75d4430a132e239b0dc2ef0 /src/synth/synth-vhdl_oper.adb | |
| parent | c9e968f395e7b1df96546d6917a721fa9cefcaa0 (diff) | |
| download | ghdl-3929ff5f232481b965ab4da4503fc515d577e4c5.tar.gz ghdl-3929ff5f232481b965ab4da4503fc515d577e4c5.tar.bz2 ghdl-3929ff5f232481b965ab4da4503fc515d577e4c5.zip | |
synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129
Diffstat (limited to 'src/synth/synth-vhdl_oper.adb')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 4a2f4d71e..274306245 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1959,7 +1959,9 @@ package body Synth.Vhdl_Oper is return Create_Value_Net (Edge, Res_Typ); end; when Iir_Predefined_Ieee_1164_Is_X_Log - | Iir_Predefined_Ieee_1164_Is_X_Slv => + | Iir_Predefined_Ieee_1164_Is_X_Slv + | Iir_Predefined_Ieee_Numeric_Std_Is_X_Sgn + | Iir_Predefined_Ieee_Numeric_Std_Is_X_Uns => -- Always false. return Create_Value_Discrete (0, Boolean_Type); when Iir_Predefined_Ieee_1164_To_Bitvector |