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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-29 08:44:22 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-29 08:44:22 +0200 |
| commit | 91f74c1d54b9e5547e38fbbacb0f25fe3b22be3a (patch) | |
| tree | 6ee69a85d684d2177259dc2464e33b913094821f /src/synth/synth-vhdl_oper.ads | |
| parent | 4542748c790c6e2b2606e6dbfe64bd0468c292b4 (diff) | |
| download | ghdl-91f74c1d54b9e5547e38fbbacb0f25fe3b22be3a.tar.gz ghdl-91f74c1d54b9e5547e38fbbacb0f25fe3b22be3a.tar.bz2 ghdl-91f74c1d54b9e5547e38fbbacb0f25fe3b22be3a.zip | |
synth-vhdl_oper: add hook for falling edge, handle aliases.
Diffstat (limited to 'src/synth/synth-vhdl_oper.ads')
| -rw-r--r-- | src/synth/synth-vhdl_oper.ads | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_oper.ads b/src/synth/synth-vhdl_oper.ads index 975244022..30d32820f 100644 --- a/src/synth/synth-vhdl_oper.ads +++ b/src/synth/synth-vhdl_oper.ads @@ -48,4 +48,5 @@ package Synth.Vhdl_Oper is function (Param : Valtyp; Res_Typ : Type_Acc) return Memtyp; Hook_Std_Rising_Edge : Eval_Predefined_Acc; + Hook_Std_Falling_Edge : Eval_Predefined_Acc; end Synth.Vhdl_Oper; |