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| author | Tristan Gingold <tgingold@free.fr> | 2023-04-19 20:50:29 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-04-19 20:55:57 +0200 |
| commit | e14a831260a11f241bb4cf393e75faae21308bbe (patch) | |
| tree | c63ac424cdc1cd42896364c3d57666e520d68320 /src/synth/synth-vhdl_stmts.adb | |
| parent | a71010fd4a37a164b68afc1b124adee21b56fd10 (diff) | |
| download | ghdl-e14a831260a11f241bb4cf393e75faae21308bbe.tar.gz ghdl-e14a831260a11f241bb4cf393e75faae21308bbe.tar.bz2 ghdl-e14a831260a11f241bb4cf393e75faae21308bbe.zip | |
synth: support aggregate when target is a dynamic slice
Fix #2418
Diffstat (limited to 'src/synth/synth-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 6fb438356..63505c9b5 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -182,6 +182,7 @@ package body Synth.Vhdl_Stmts is Sl_Voff : Net; Sl_Off : Value_Offsets; Err : Boolean; + Arr_Typ : Type_Acc; begin if Dest_Base.Val /= null then Strip_Const (Dest_Base); @@ -218,7 +219,8 @@ package body Synth.Vhdl_Stmts is (Get_Build (Syn_Inst), Dest_Dyn.Voff, Sl_Voff); Set_Location (Dest_Dyn.Voff, Pfx); end if; - Dest_Typ := Create_Slice_Type (Res_Bnd.Len, El_Typ); + Arr_Typ := Create_Array_Type (Res_Bnd, False, True, El_Typ); + Dest_Typ := Create_Slice_Type (Arr_Typ, Res_Bnd.Len, El_Typ); end if; end Synth_Assignment_Prefix_Slice_Name; |