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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-08 07:52:43 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-08 07:52:43 +0200 |
| commit | c5fbc11795004074b9f2f52e94e13d5907f1c95b (patch) | |
| tree | 8fbe2aa0d82011bb95d67a3cc3b2ffd205b6b3e7 /src/synth/synthesis.adb | |
| parent | 2a21ee61dd73224bec023b3a541c9d4ddaee0f88 (diff) | |
| download | ghdl-c5fbc11795004074b9f2f52e94e13d5907f1c95b.tar.gz ghdl-c5fbc11795004074b9f2f52e94e13d5907f1c95b.tar.bz2 ghdl-c5fbc11795004074b9f2f52e94e13d5907f1c95b.zip | |
synth: support conditional signal assignments.
Diffstat (limited to 'src/synth/synthesis.adb')
| -rw-r--r-- | src/synth/synthesis.adb | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb index 7f42d018c..cd72354e4 100644 --- a/src/synth/synthesis.adb +++ b/src/synth/synthesis.adb @@ -221,10 +221,12 @@ package body Synthesis is end loop; Synth_Declarations (Syn_Inst, Get_Declaration_Chain (Entity)); - Synth_Statements (Syn_Inst, Get_Concurrent_Statement_Chain (Entity)); + Synth_Concurrent_Statements + (Syn_Inst, Get_Concurrent_Statement_Chain (Entity)); Synth_Declarations (Syn_Inst, Get_Declaration_Chain (Arch)); - Synth_Statements (Syn_Inst, Get_Concurrent_Statement_Chain (Arch)); + Synth_Concurrent_Statements + (Syn_Inst, Get_Concurrent_Statement_Chain (Arch)); -- Remove unused gates. This is not only an optimization but also -- a correctness point: there might be some unsynthesizable gates, like |