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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-11 06:29:18 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-11 06:37:28 +0200 |
| commit | 0e5e045b01b6425ae3551ad1c463d8f8f57907d7 (patch) | |
| tree | ee62774425173e2bbbe0fdc05222f0afece69084 /src/synth | |
| parent | 99344d16bac958ce9abbeaa78f5efd82c7ea612a (diff) | |
| download | ghdl-0e5e045b01b6425ae3551ad1c463d8f8f57907d7.tar.gz ghdl-0e5e045b01b6425ae3551ad1c463d8f8f57907d7.tar.bz2 ghdl-0e5e045b01b6425ae3551ad1c463d8f8f57907d7.zip | |
synth: improve support of negative integer values.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-context.adb | 37 | ||||
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 7 |
2 files changed, 29 insertions, 15 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb index 12ad60ed4..adc2277a3 100644 --- a/src/synth/synth-context.adb +++ b/src/synth/synth-context.adb @@ -373,20 +373,29 @@ package body Synth.Context is I1 => Get_Net (Val.M_T)); end; when Value_Discrete => - if Val.Typ.Kind = Type_Bit then - declare - V : Logvec_Array (0 .. 0) := (0 => (0, 0)); - Res : Net; - begin - Value2net (Val, 1, V, Res); - return Res; - end; - elsif Val.Typ.W <= 32 then - return Build_Const_UB32 - (Build_Context, Uns32 (Val.Scal), Val.Typ.W); - else - raise Internal_Error; - end if; + case Val.Typ.Kind is + when Type_Bit => + declare + V : Logvec_Array (0 .. 0) := (0 => (0, 0)); + Res : Net; + begin + Value2net (Val, 1, V, Res); + return Res; + end; + when Type_Discrete => + if Val.Typ.W <= 32 then + declare + V : Uns32; + begin + V := Uns32 (To_Uns64 (Val.Scal) and 16#ffff_ffff#); + return Build_Const_UB32 (Build_Context, V, Val.Typ.W); + end; + else + raise Internal_Error; + end if; + when others => + raise Internal_Error; + end case; when Value_Const_Array | Value_Const_Record => declare diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 61bf31534..13d69c984 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -222,7 +222,12 @@ package body Synth.Disp_Vhdl is when Iir_Kind_Integer_Type_Definition => -- FIXME: signed or unsigned ? W := Typ.W; - Put (" " & Pfx & " <= to_integer (unsigned"); + Put (" " & Pfx & " <= to_integer ("); + if Typ.Drange.Is_Signed then + Put ("signed"); + else + Put ("unsigned"); + end if; if W = 1 then Put ("'(0 => "); else |