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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-04 20:12:39 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-04 20:12:39 +0200 |
| commit | 2229c2b97868887a2d5dc8c423a4cfb3f2ec15ac (patch) | |
| tree | 6c33aeff58dc43cd32c1410a0c20c39336b2baf4 /src/synth | |
| parent | b8fc71301c28d18aa8b8c15c49f4c67103afedc2 (diff) | |
| download | ghdl-2229c2b97868887a2d5dc8c423a4cfb3f2ec15ac.tar.gz ghdl-2229c2b97868887a2d5dc8c423a4cfb3f2ec15ac.tar.bz2 ghdl-2229c2b97868887a2d5dc8c423a4cfb3f2ec15ac.zip | |
netlists-disp_vhdl: handle lsl, rol, asr, nand, nor.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index a1126a852..2f6c63628 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -764,6 +764,19 @@ package body Netlists.Disp_Vhdl is when Id_Srem => Disp_Template (" \o0 <= std_logic_vector (\si0 rem \si1);" & NL, Inst); + when Id_Lsl => + Disp_Template + (" \o0 <= std_logic_vector " + & "(shift_left (\ui0, to_integer (\ui1)));" & NL, Inst); + when Id_Asr => + Disp_Template + (" \o0 <= std_logic_vector " + & "(shift_left (\si0, to_integer (\ui1)));" & NL, Inst); + when Id_Rol => + Disp_Template + (" \o0 <= std_logic_vector " + & "(rotate_left (\ui0, to_integer (\ui1)));" & NL, Inst); + when Id_Ult => Disp_Template (" \o0 <= '1' when \ui0 < \ui1 else '0';" & NL, Inst); @@ -800,6 +813,11 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= \i0 and \i1;" & NL, Inst); when Id_Xor => Disp_Template (" \o0 <= \i0 xor \i1;" & NL, Inst); + when Id_Nor => + Disp_Template (" \o0 <= \i0 nor \i1;" & NL, Inst); + when Id_Nand => + Disp_Template (" \o0 <= \i0 nand \i1;" & NL, Inst); + when Id_Concat2 => declare Wd : constant Width := Get_Width (Get_Output (Inst, 0)); |