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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-16 08:07:01 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-16 08:07:01 +0200 |
| commit | 23bb49eb1f24c65effe07377d8748687e5a668bf (patch) | |
| tree | afb4fde1a931fbe560bd5cd2949afeba6f55cc48 /src/synth | |
| parent | b9fc9fbf389a24201d05d649daeac782c864404e (diff) | |
| download | ghdl-23bb49eb1f24c65effe07377d8748687e5a668bf.tar.gz ghdl-23bb49eb1f24c65effe07377d8748687e5a668bf.tar.bz2 ghdl-23bb49eb1f24c65effe07377d8748687e5a668bf.zip | |
synth: handle inout ports with default values. For #1312
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 3 | ||||
| -rw-r--r-- | src/synth/synth-environment.adb | 6 |
2 files changed, 7 insertions, 2 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index be60f4c19..84a53c866 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -867,7 +867,8 @@ package body Netlists.Disp_Vhdl is null; when Id_Output => Disp_Template (" \o0 <= \i0; -- (output)" & NL, Inst); - when Id_Inout => + when Id_Inout + | Id_Iinout => -- Gates inout are special: output 1 must be connected to an -- output (with the is_inout flag set) of the module. Disp_Template (" \o1 <= \i0; -- (inout - port)" & NL, Inst); diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index 4e789ef05..db76e286a 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -848,7 +848,11 @@ package body Synth.Environment is then Warning_Msg_Synth (+Wire_Rec.Decl, "no assignment for %n", +Wire_Rec.Decl); - Value := Build_Const_Z (Ctxt, Get_Width (Wire_Rec.Gate)); + if Get_Id (Gate_Inst) = Gates.Id_Iinout then + Value := Get_Input_Net (Gate_Inst, 1); + else + Value := Build_Const_Z (Ctxt, Get_Width (Wire_Rec.Gate)); + end if; else return; end if; |