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authorTristan Gingold <tgingold@free.fr>2020-07-02 22:07:33 +0200
committerTristan Gingold <tgingold@free.fr>2020-07-02 22:07:33 +0200
commit2c832dae31499fa8e8bd8d44d5f8abecae687f2e (patch)
treed1ee29f4710baf4782b92cd9928c6642c8a2093a /src/synth
parent38848c600d7d15940ccc39aa7f764547a37b936a (diff)
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netlists-disp_vhdl: display inout ports as inout.
Diffstat (limited to 'src/synth')
-rw-r--r--src/synth/netlists-disp_vhdl.adb10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 6a013ed93..4b61b4bd4 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -1562,7 +1562,7 @@ package body Netlists.Disp_Vhdl is
when Port_Out =>
Put ("out");
when Port_Inout =>
- raise Internal_Error;
+ Put ("inout");
end case;
Put (' ');
Put_Type (Desc.W);
@@ -1571,13 +1571,19 @@ package body Netlists.Disp_Vhdl is
procedure Disp_Entity_Ports (M : Module)
is
First : Boolean;
+ Desc : Port_Desc;
begin
First := True;
for I in 1 .. Get_Nbr_Inputs (M) loop
Disp_Entity_Port (Get_Input_Desc (M, I - 1), Port_In, First);
end loop;
for I in 1 .. Get_Nbr_Outputs (M) loop
- Disp_Entity_Port (Get_Output_Desc (M, I - 1), Port_Out, First);
+ Desc := Get_Output_Desc (M, I - 1);
+ if Desc.Is_Inout then
+ Disp_Entity_Port (Desc, Port_Inout, First);
+ else
+ Disp_Entity_Port (Desc, Port_Out, First);
+ end if;
end loop;
if not First then
Put_Line (");");