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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-21 18:09:29 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-21 18:09:29 +0200 |
| commit | 6b39e5fa8d8abb742df7ffac50b115034994f35e (patch) | |
| tree | 35efa00aeec413ec4e0e644a786f6a1aae475854 /src/synth | |
| parent | f9f0002babb98fe751f3b71ef009a79e60057f06 (diff) | |
| download | ghdl-6b39e5fa8d8abb742df7ffac50b115034994f35e.tar.gz ghdl-6b39e5fa8d8abb742df7ffac50b115034994f35e.tar.bz2 ghdl-6b39e5fa8d8abb742df7ffac50b115034994f35e.zip | |
synth-oper: fix handle of add/sub with std_logic.
The operand is simply 0-extended.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-oper.adb | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 9ab0fd6ee..711833f04 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -876,32 +876,32 @@ package body Synth.Oper is -- "+" (Natural, Unsigned) return Synth_Dyadic_Nat_Uns (Ctxt, Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns - | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns => + | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log + | Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log + | Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn => -- "+" (Unsigned, Unsigned) return Synth_Dyadic_Uns_Uns (Ctxt, Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int - | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int => + | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int => -- "+" (Signed, Integer) return Synth_Dyadic_Sgn_Int (Ctxt, Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv => + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv => -- "+" (Integer, Signed) return Synth_Dyadic_Int_Sgn (Ctxt, Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn - | Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log - | Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv - | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv => + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv + | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv => -- "+" (Signed, Signed) return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Add, Left, Right, Expr); @@ -910,12 +910,15 @@ package body Synth.Oper is -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Ctxt, Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log + | Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns => + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn => -- "-" (Unsigned, Unsigned) return Synth_Dyadic_Uns_Uns (Ctxt, Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns => @@ -929,10 +932,7 @@ package body Synth.Oper is -- "-" (Integer, Signed) return Synth_Dyadic_Int_Sgn (Ctxt, Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn - | Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log - | Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv => -- "-" (Signed, Signed) return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Sub, Left, Right, Expr); |