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| author | Tristan Gingold <tgingold@free.fr> | 2020-10-07 18:55:30 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-10-07 18:55:30 +0200 |
| commit | 6e303efe5b1e3b6ab9f4f37d2e35c645496c03d7 (patch) | |
| tree | 3faa0d6172078e5ffd080c00db74ab8bebc86533 /src/synth | |
| parent | 4a7ec846e9f18bba17d1339de4317fa76c145978 (diff) | |
| download | ghdl-6e303efe5b1e3b6ab9f4f37d2e35c645496c03d7.tar.gz ghdl-6e303efe5b1e3b6ab9f4f37d2e35c645496c03d7.tar.bz2 ghdl-6e303efe5b1e3b6ab9f4f37d2e35c645496c03d7.zip | |
synth-expr: improve error message for length mismatch
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-expr.adb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 3cc92cf1d..2282d48b2 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -23,6 +23,7 @@ with Name_Table; with Std_Names; with Str_Table; with Mutils; use Mutils; +with Errorout; use Errorout; with Vhdl.Types; with Vhdl.Ieee.Std_Logic_1164; use Vhdl.Ieee.Std_Logic_1164; @@ -829,7 +830,9 @@ package body Synth.Expr is pragma Assert (Vtype.Kind = Type_Vector or Vtype.Kind = Type_Slice); if Dtype.W /= Vtype.W then - Error_Msg_Synth (+Loc, "mismatching vector length"); + Error_Msg_Synth + (+Loc, "mismatching vector length; got %v, expect %v", + (Errorout."+" (Vtype.W), +Dtype.W)); return No_Valtyp; end if; if Bounds then |