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authorTristan Gingold <tgingold@free.fr>2020-05-03 22:18:18 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-04 19:04:11 +0200
commit6ff7ef51aec7c1d653dab142aa0e5cda170e9f29 (patch)
tree2fdea222c454ec44d641efbc79a53d1da243d5f6 /src/synth
parent6d6ee6778edcbca12bc322839c061fe788bb86ba (diff)
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synth: reduce use of global context.
Diffstat (limited to 'src/synth')
-rw-r--r--src/synth/synth-aggr.adb18
-rw-r--r--src/synth/synth-context.adb49
-rw-r--r--src/synth/synth-context.ads17
-rw-r--r--src/synth/synth-decls.adb29
-rw-r--r--src/synth/synth-environment.adb19
-rw-r--r--src/synth/synth-expr.adb64
-rw-r--r--src/synth/synth-expr.ads4
-rw-r--r--src/synth/synth-insts.adb18
-rw-r--r--src/synth/synth-oper.adb340
-rw-r--r--src/synth/synth-stmts.adb72
10 files changed, 341 insertions, 289 deletions
diff --git a/src/synth/synth-aggr.adb b/src/synth/synth-aggr.adb
index 103a62681..6840734ca 100644
--- a/src/synth/synth-aggr.adb
+++ b/src/synth/synth-aggr.adb
@@ -21,6 +21,7 @@
with Types; use Types;
with Netlists.Utils; use Netlists.Utils;
+with Netlists.Builders; use Netlists.Builders;
with Vhdl.Errors; use Vhdl.Errors;
@@ -106,6 +107,7 @@ package body Synth.Aggr is
Const_P : out Boolean;
Err_P : out boolean)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Bound : constant Bound_Type := Get_Array_Bound (Typ, Dim);
El_Typ : constant Type_Acc := Get_Array_Element (Typ);
Stride : constant Nat32 := Strides (Dim);
@@ -124,7 +126,7 @@ package body Synth.Aggr is
if Dim = Strides'Last then
Val := Synth_Expression_With_Type (Syn_Inst, Value, El_Typ, En);
- Val := Synth_Subtype_Conversion (Val, El_Typ, False, Value);
+ Val := Synth_Subtype_Conversion (Ctxt, Val, El_Typ, False, Value);
pragma Assert (Res (Pos) = No_Valtyp);
Res (Pos) := Val;
if Val = No_Valtyp then
@@ -303,6 +305,7 @@ package body Synth.Aggr is
Rec : Valtyp_Array_Acc;
Const_P : out Boolean)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
El_List : constant Node_Flist :=
Get_Elements_Declaration_List (Get_Type (Aggr));
Value : Node;
@@ -321,7 +324,7 @@ package body Synth.Aggr is
if Const_P and not Is_Static (Val.Val) then
Const_P := False;
end if;
- Val := Synth_Subtype_Conversion (Val, El_Type, False, Value);
+ Val := Synth_Subtype_Conversion (Ctxt, Val, El_Type, False, Value);
-- Put in reverse order. The first record element (at position 0)
-- will be the LSB, so the last element of REC.
Rec (Nat32 (Rec'Last - Pos)) := Val;
@@ -359,7 +362,8 @@ package body Synth.Aggr is
end loop;
end Fill_Record_Aggregate;
- function Valtyp_Array_To_Net (Tab : Valtyp_Array) return Net
+ function Valtyp_Array_To_Net (Ctxt : Context_Acc; Tab : Valtyp_Array)
+ return Net
is
Res : Net;
Arr : Net_Array_Acc;
@@ -370,7 +374,7 @@ package body Synth.Aggr is
for I in Arr'Range loop
if Tab (I).Val /= null then
Idx := Idx + 1;
- Arr (Idx) := Get_Net (Tab (I));
+ Arr (Idx) := Get_Net (Ctxt, Tab (I));
end if;
end loop;
Concat_Array (Arr (1 .. Idx), Res);
@@ -383,6 +387,7 @@ package body Synth.Aggr is
En : Net;
Aggr_Type : Type_Acc) return Valtyp
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Strides : constant Stride_Array := Fill_Stride (Aggr_Type);
Flen : constant Iir_Index32 := Get_Array_Flat_Length (Aggr_Type);
Tab_Res : Valtyp_Array_Acc;
@@ -417,7 +422,7 @@ package body Synth.Aggr is
end;
else
Res := Create_Value_Net
- (Valtyp_Array_To_Net (Tab_Res.all), Aggr_Type);
+ (Valtyp_Array_To_Net (Ctxt, Tab_Res.all), Aggr_Type);
end if;
Free_Valtyp_Array (Tab_Res);
@@ -430,6 +435,7 @@ package body Synth.Aggr is
En : Net;
Aggr_Type : Type_Acc) return Valtyp
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Tab_Res : Valtyp_Array_Acc;
Res : Valtyp;
Const_P : Boolean;
@@ -448,7 +454,7 @@ package body Synth.Aggr is
end loop;
else
Res := Create_Value_Net
- (Valtyp_Array_To_Net (Tab_Res.all), Aggr_Type);
+ (Valtyp_Array_To_Net (Ctxt, Tab_Res.all), Aggr_Type);
end if;
Free_Valtyp_Array (Tab_Res);
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 822acd731..0893e9c7c 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -26,7 +26,6 @@ with Types_Utils; use Types_Utils;
with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Utils;
-with Netlists.Builders; use Netlists.Builders;
with Netlists.Folds; use Netlists.Folds;
with Synth.Expr; use Synth.Expr;
@@ -429,7 +428,8 @@ package body Synth.Context is
end loop;
end Is_Full;
- procedure Value2net (Val : Memtyp;
+ procedure Value2net (Ctxt : Context_Acc;
+ Val : Memtyp;
Off : Uns32;
W : Width;
Vec : in out Logvec_Array;
@@ -449,35 +449,34 @@ package body Synth.Context is
-- Then convert logvec to net.
if W = 0 then
-- For null range (like the null string literal "")
- Res := Build_Const_UB32 (Build_Context, 0, 0);
+ Res := Build_Const_UB32 (Ctxt, 0, 0);
elsif W <= 32 then
-- 32 bit result.
if not Has_Zx then
- Res := Build_Const_UB32 (Build_Context, Vec (0).Val, W);
+ Res := Build_Const_UB32 (Ctxt, Vec (0).Val, W);
elsif Vec (0).Val = 0 and then Sext (Vec (0).Zx, Natural (W)) = not 0
then
- Res := Build_Const_Z (Build_Context, W);
+ Res := Build_Const_Z (Ctxt, W);
else
- Res := Build_Const_UL32
- (Build_Context, Vec (0).Val, Vec (0).Zx, W);
+ Res := Build_Const_UL32 (Ctxt, Vec (0).Val, Vec (0).Zx, W);
end if;
return;
else
Is_Full (Vec, Is_0, Is_X, Is_Z);
if Is_0 then
- Res := Build_Const_UB32 (Build_Context, 0, W);
+ Res := Build_Const_UB32 (Ctxt, 0, W);
elsif Is_X then
- Res := Build_Const_X (Build_Context, W);
+ Res := Build_Const_X (Ctxt, W);
elsif Is_Z then
- Res := Build_Const_Z (Build_Context, W);
+ Res := Build_Const_Z (Ctxt, W);
elsif not Has_Zx then
- Inst := Build_Const_Bit (Build_Context, W);
+ Inst := Build_Const_Bit (Ctxt, W);
for I in Vec'Range loop
Set_Param_Uns32 (Inst, Param_Idx (I), Vec (I).Val);
end loop;
Res := Get_Output (Inst, 0);
else
- Inst := Build_Const_Log (Build_Context, W);
+ Inst := Build_Const_Log (Ctxt, W);
for I in Vec'Range loop
Set_Param_Uns32 (Inst, Param_Idx (2 * I), Vec (I).Val);
Set_Param_Uns32 (Inst, Param_Idx (2 * I + 1), Vec (I).Zx);
@@ -487,8 +486,8 @@ package body Synth.Context is
end if;
end Value2net;
- function Get_Partial_Memtyp_Net (Val : Memtyp; Off : Uns32; Wd : Width)
- return Net
+ function Get_Partial_Memtyp_Net
+ (Ctxt : Context_Acc; Val : Memtyp; Off : Uns32; Wd : Width) return Net
is
Nd : constant Digit_Index := Digit_Index ((Wd + 31) / 32);
Res : Net;
@@ -498,7 +497,7 @@ package body Synth.Context is
Vecp : Logvec_Array_Acc;
begin
Vecp := new Logvec_Array'(0 .. Nd - 1 => (0, 0));
- Value2net (Val, Off, Wd, Vecp.all, Res);
+ Value2net (Ctxt, Val, Off, Wd, Vecp.all, Res);
Free_Logvec_Array (Vecp);
return Res;
end;
@@ -506,22 +505,22 @@ package body Synth.Context is
declare
Vec : Logvec_Array (0 .. Nd - 1) := (others => (0, 0));
begin
- Value2net (Val, Off, Wd, Vec, Res);
+ Value2net (Ctxt, Val, Off, Wd, Vec, Res);
return Res;
end;
end if;
end Get_Partial_Memtyp_Net;
- function Get_Memtyp_Net (Val : Memtyp) return Net is
+ function Get_Memtyp_Net (Ctxt : Context_Acc; Val : Memtyp) return Net is
begin
- return Get_Partial_Memtyp_Net (Val, 0, Val.Typ.W);
+ return Get_Partial_Memtyp_Net (Ctxt, Val, 0, Val.Typ.W);
end Get_Memtyp_Net;
- function Get_Net (Val : Valtyp) return Net is
+ function Get_Net (Ctxt : Context_Acc; Val : Valtyp) return Net is
begin
case Val.Val.Kind is
when Value_Wire =>
- return Get_Current_Value (Build_Context, Val.Val.W);
+ return Get_Current_Value (Ctxt, Val.Val.W);
when Value_Net =>
return Val.Val.N;
when Value_Alias =>
@@ -529,23 +528,23 @@ package body Synth.Context is
Res : Net;
begin
if Val.Val.A_Obj.Kind = Value_Wire then
- Res := Get_Current_Value (Build_Context, Val.Val.A_Obj.W);
+ Res := Get_Current_Value (Ctxt, Val.Val.A_Obj.W);
return Build2_Extract
- (Build_Context, Res, Val.Val.A_Off.Net_Off, Val.Typ.W);
+ (Ctxt, Res, Val.Val.A_Off.Net_Off, Val.Typ.W);
else
pragma Assert (Val.Val.A_Off.Net_Off = 0);
- return Get_Net ((Val.Typ, Val.Val.A_Obj));
+ return Get_Net (Ctxt, (Val.Typ, Val.Val.A_Obj));
end if;
end;
when Value_Const =>
if Val.Val.C_Net = No_Net then
- Val.Val.C_Net := Get_Net ((Val.Typ, Val.Val.C_Val));
+ Val.Val.C_Net := Get_Net (Ctxt, (Val.Typ, Val.Val.C_Val));
Locations.Set_Location (Get_Net_Parent (Val.Val.C_Net),
Get_Location (Val.Val.C_Loc));
end if;
return Val.Val.C_Net;
when Value_Memory =>
- return Get_Memtyp_Net (Get_Memtyp (Val));
+ return Get_Memtyp_Net (Ctxt, Get_Memtyp (Val));
when others =>
raise Internal_Error;
end case;
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index 6196257b8..2c7dd78ae 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -21,7 +21,7 @@
with Types; use Types;
with Netlists; use Netlists;
-with Netlists.Builders;
+with Netlists.Builders; use Netlists.Builders;
with Vhdl.Annotations; use Vhdl.Annotations;
with Vhdl.Nodes; use Vhdl.Nodes;
@@ -38,7 +38,7 @@ package Synth.Context is
type Synth_Instance_Acc is access Synth_Instance_Type;
-- Global context.
- Build_Context : Netlists.Builders.Context_Acc;
+ Build_Context : Context_Acc;
function Get_Instance_By_Scope
(Syn_Inst: Synth_Instance_Acc; Scope: Sim_Info_Acc)
@@ -71,8 +71,7 @@ package Synth.Context is
function Get_Sname (Inst : Synth_Instance_Acc) return Sname;
pragma Inline (Get_Sname);
- function Get_Build (Inst : Synth_Instance_Acc)
- return Netlists.Builders.Context_Acc;
+ function Get_Build (Inst : Synth_Instance_Acc) return Context_Acc;
pragma Inline (Get_Build);
function Get_Top_Module (Inst : Synth_Instance_Acc) return Module;
@@ -120,10 +119,10 @@ package Synth.Context is
-- Get a net from a scalar/vector value. This will automatically create
-- a net for literals.
- function Get_Net (Val : Valtyp) return Net;
- function Get_Partial_Memtyp_Net (Val : Memtyp; Off : Uns32; Wd : Width)
- return Net;
- function Get_Memtyp_Net (Val : Memtyp) return Net;
+ function Get_Net (Ctxt : Context_Acc; Val : Valtyp) return Net;
+ function Get_Partial_Memtyp_Net
+ (Ctxt : Context_Acc; Val : Memtyp; Off : Uns32; Wd : Width) return Net;
+ function Get_Memtyp_Net (Ctxt : Context_Acc; Val : Memtyp) return Net;
function Get_Package_Object
(Syn_Inst : Synth_Instance_Acc; Pkg : Node) return Synth_Instance_Acc;
@@ -162,7 +161,7 @@ private
type Objects_Array is array (Object_Slot_Type range <>) of Obj_Type;
type Base_Instance_Type is limited record
- Builder : Netlists.Builders.Context_Acc;
+ Builder : Context_Acc;
Top_Module : Module;
Cur_Module : Module;
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 5bd535215..d3a9cc13f 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -46,6 +46,7 @@ package body Synth.Decls is
procedure Create_Var_Wire
(Syn_Inst : Synth_Instance_Acc; Decl : Iir; Init : Valtyp)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Vt : constant Valtyp := Get_Value (Syn_Inst, Decl);
Value : Net;
Ival : Net;
@@ -59,11 +60,11 @@ package body Synth.Decls is
Name := New_Sname_User (Get_Identifier (Decl),
Get_Sname (Syn_Inst));
if Init /= No_Valtyp then
- Ival := Get_Net (Init);
+ Ival := Get_Net (Ctxt, Init);
pragma Assert (Get_Width (Ival) = W);
- Value := Build_Isignal (Get_Build (Syn_Inst), Name, Ival);
+ Value := Build_Isignal (Ctxt, Name, Ival);
else
- Value := Build_Signal (Get_Build (Syn_Inst), Name, W);
+ Value := Build_Signal (Ctxt, Name, W);
end if;
Set_Location (Value, Decl);
Set_Wire_Gate (Vt.Val.W, Value);
@@ -467,6 +468,7 @@ package body Synth.Decls is
Is_Subprg : Boolean;
Last_Type : in out Node)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Deferred_Decl : constant Node := Get_Deferred_Declaration (Decl);
First_Decl : Node;
Decl_Type : Node;
@@ -514,7 +516,7 @@ package body Synth.Decls is
Set_Error (Syn_Inst);
return;
end if;
- Val := Synth_Subtype_Conversion (Val, Obj_Type, True, Decl);
+ Val := Synth_Subtype_Conversion (Ctxt, Val, Obj_Type, True, Decl);
-- For constant functions, the value must be constant.
pragma Assert (not Get_Instance_Const (Syn_Inst)
or else Is_Static (Val.Val));
@@ -659,6 +661,7 @@ package body Synth.Decls is
Assoc_Chain : Node;
En : Net)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Inter : Node;
Inter_Type : Type_Acc;
Assoc : Node;
@@ -688,7 +691,7 @@ package body Synth.Decls is
raise Internal_Error;
end case;
- Val := Synth_Subtype_Conversion (Val, Inter_Type, True, Assoc);
+ Val := Synth_Subtype_Conversion (Ctxt, Val, Inter_Type, True, Assoc);
pragma Assert (Is_Static (Val.Val));
@@ -736,6 +739,7 @@ package body Synth.Decls is
En : Net;
Is_Subprg : Boolean)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Def : constant Node := Get_Default_Value (Decl);
Decl_Type : constant Node := Get_Type (Decl);
Init : Valtyp;
@@ -762,7 +766,8 @@ package body Synth.Decls is
else
if Is_Valid (Def) then
Init := Synth_Expression_With_Type (Syn_Inst, Def, Obj_Typ, En);
- Init := Synth_Subtype_Conversion (Init, Obj_Typ, False, Decl);
+ Init := Synth_Subtype_Conversion
+ (Ctxt, Init, Obj_Typ, False, Decl);
if not Is_Subprg
and then not Is_Static (Init.Val)
then
@@ -784,8 +789,7 @@ package body Synth.Decls is
if Is_Static (Init.Val) then
Phi_Assign_Static (Wid, Get_Memtyp (Init));
else
- Phi_Assign_Net
- (Get_Build (Syn_Inst), Wid, Get_Net (Init), 0);
+ Phi_Assign_Net (Ctxt, Wid, Get_Net (Ctxt, Init), 0);
end if;
end if;
end if;
@@ -795,6 +799,7 @@ package body Synth.Decls is
procedure Synth_Signal_Declaration (Syn_Inst : Synth_Instance_Acc;
Decl : Node)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Def : constant Iir := Get_Default_Value (Decl);
-- Slot : constant Object_Slot_Type := Get_Info (Decl).Slot;
Init : Valtyp;
@@ -805,7 +810,7 @@ package body Synth.Decls is
if Is_Valid (Def) then
Obj_Typ := Get_Subtype_Object (Syn_Inst, Get_Type (Decl));
Init := Synth_Expression_With_Type (Syn_Inst, Def, Obj_Typ, No_Net);
- Init := Synth_Subtype_Conversion (Init, Obj_Typ, False, Decl);
+ Init := Synth_Subtype_Conversion (Ctxt, Init, Obj_Typ, False, Decl);
if not Is_Static (Init.Val) then
Error_Msg_Synth (+Decl, "signals cannot be used in default value "
& "of a signal");
@@ -819,6 +824,7 @@ package body Synth.Decls is
procedure Synth_Object_Alias_Declaration
(Syn_Inst : Synth_Instance_Acc; Decl : Node; En : Net)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Atype : constant Node := Get_Declaration_Type (Decl);
Off : Value_Offsets;
Dyn : Stmts.Dyn_Name;
@@ -842,14 +848,13 @@ package body Synth.Decls is
-- Object is a net if it is not writable. Extract the
-- bits for the alias.
Res := Create_Value_Net
- (Build2_Extract (Get_Build (Syn_Inst),
- Base.Val.N, Off.Net_Off, Typ.W),
+ (Build2_Extract (Ctxt, Base.Val.N, Off.Net_Off, Typ.W),
Typ);
else
Res := Create_Value_Alias (Base, Off, Typ);
end if;
if Obj_Typ /= null then
- Res := Synth_Subtype_Conversion (Res, Obj_Typ, True, Decl);
+ Res := Synth_Subtype_Conversion (Ctxt, Res, Obj_Typ, True, Decl);
end if;
Create_Object (Syn_Inst, Decl, Res);
end Synth_Object_Alias_Declaration;
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb
index a48ae0119..5a24fd4ba 100644
--- a/src/synth/synth-environment.adb
+++ b/src/synth/synth-environment.adb
@@ -370,7 +370,7 @@ package body Synth.Environment is
raise Internal_Error;
when True =>
-- Create a net. No inference to do.
- Res := Synth.Context.Get_Memtyp_Net (Asgn_Rec.Val.Val);
+ Res := Synth.Context.Get_Memtyp_Net (Ctxt, Asgn_Rec.Val.Val);
Add_Conc_Assign (Wid, Res, 0, Stmt);
when False =>
P := Asgn_Rec.Val.Asgns;
@@ -948,7 +948,7 @@ package body Synth.Environment is
end case;
if Asgn_Rec.Val.Is_Static = True then
- return Synth.Context.Get_Memtyp_Net (Asgn_Rec.Val.Val);
+ return Synth.Context.Get_Memtyp_Net (Ctxt, Asgn_Rec.Val.Val);
end if;
-- Cannot be empty.
@@ -993,7 +993,7 @@ package body Synth.Environment is
-- Get the current value of W for WD bits at offset OFF.
function Get_Current_Assign_Value
- (Ctxt : Builders.Context_Acc; Wid : Wire_Id; Off : Uns32; Wd : Width)
+ (Ctxt : Context_Acc; Wid : Wire_Id; Off : Uns32; Wd : Width)
return Net
is
Wire_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Wid);
@@ -1011,7 +1011,7 @@ package body Synth.Environment is
-- If the current value is static, just return it.
if Get_Assign_Is_Static (First_Seq) then
return Context.Get_Partial_Memtyp_Net
- (Get_Assign_Static_Val (First_Seq), Off, Wd);
+ (Ctxt, Get_Assign_Static_Val (First_Seq), Off, Wd);
end if;
-- If the range is the same as the seq assign, return the value.
@@ -1097,9 +1097,9 @@ package body Synth.Environment is
end if;
if Get_Assign_Is_Static (Seq) then
-- Extract from static value.
- Append
- (Vec, Context.Get_Partial_Memtyp_Net
- (Get_Assign_Static_Val (Seq), Cur_Off, Cur_Wd));
+ Append (Vec, Context.Get_Partial_Memtyp_Net
+ (Ctxt, Get_Assign_Static_Val (Seq),
+ Cur_Off, Cur_Wd));
exit;
end if;
P := Get_Assign_Partial (Seq);
@@ -1210,7 +1210,8 @@ package body Synth.Environment is
when Unknown =>
null;
when True =>
- N (I) := Context.Get_Partial_Memtyp_Net (P (I).Val, Off, Wd);
+ N (I) := Context.Get_Partial_Memtyp_Net
+ (Ctxt, P (I).Val, Off, Wd);
when False =>
if Get_Partial_Offset (P (I).Asgns) <= Off then
declare
@@ -1734,7 +1735,7 @@ package body Synth.Environment is
N : Net;
Pa : Partial_Assign;
begin
- N := Synth.Context.Get_Memtyp_Net (Asgn_Rec.Val.Val);
+ N := Synth.Context.Get_Memtyp_Net (Ctxt, Asgn_Rec.Val.Val);
Pa := New_Partial_Assign (N, 0);
Asgn_Rec.Val := (Is_Static => False, Asgns => Pa);
end;
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index b3b286d78..6e4fd031b 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -32,7 +32,6 @@ with Vhdl.Evaluation; use Vhdl.Evaluation;
with Vhdl.Annotations; use Vhdl.Annotations;
with Netlists.Gates; use Netlists.Gates;
-with Netlists.Builders; use Netlists.Builders;
with Netlists.Folds; use Netlists.Folds;
with Netlists.Utils; use Netlists.Utils;
@@ -338,7 +337,8 @@ package body Synth.Expr is
end Value2logvec;
-- Resize for a discrete value.
- function Synth_Resize (Val : Valtyp; W : Width; Loc : Node) return Net
+ function Synth_Resize
+ (Ctxt : Context_Acc; Val : Valtyp; W : Width; Loc : Node) return Net
is
Wn : constant Width := Val.Typ.W;
N : Net;
@@ -351,23 +351,22 @@ package body Synth.Expr is
-- Optimization: resize directly.
V := Read_Discrete (Val);
if Val.Typ.Drange.Is_Signed then
- Res := Build2_Const_Int (Build_Context, V, W);
+ Res := Build2_Const_Int (Ctxt, V, W);
else
- Res := Build2_Const_Uns (Build_Context, To_Uns64 (V), W);
+ Res := Build2_Const_Uns (Ctxt, To_Uns64 (V), W);
end if;
Set_Location (Res, Loc);
return Res;
end if;
- N := Get_Net (Val);
+ N := Get_Net (Ctxt, Val);
if Wn > W then
- return Build2_Trunc (Build_Context, Id_Utrunc, N, W,
- Get_Location (Loc));
+ return Build2_Trunc (Ctxt, Id_Utrunc, N, W, Get_Location (Loc));
elsif Wn < W then
if Val.Typ.Drange.Is_Signed then
- Res := Build_Extend (Build_Context, Id_Sextend, N, W);
+ Res := Build_Extend (Ctxt, Id_Sextend, N, W);
else
- Res := Build_Extend (Build_Context, Id_Uextend, N, W);
+ Res := Build_Extend (Ctxt, Id_Uextend, N, W);
end if;
Set_Location (Res, Loc);
return Res;
@@ -710,7 +709,8 @@ package body Synth.Expr is
end case;
end Reshape_Value;
- function Synth_Subtype_Conversion (Vt : Valtyp;
+ function Synth_Subtype_Conversion (Ctxt : Context_Acc;
+ Vt : Valtyp;
Dtype : Type_Acc;
Bounds : Boolean;
Loc : Source.Syn_Src)
@@ -750,18 +750,18 @@ package body Synth.Expr is
(Get_Static_Discrete (Vt), Dtype);
end if;
- N := Get_Net (Vt);
+ N := Get_Net (Ctxt, Vt);
if Vtype.Drange.Is_Signed then
N := Build2_Sresize
- (Build_Context, N, Dtype.W, Get_Location (Loc));
+ (Ctxt, N, Dtype.W, Get_Location (Loc));
else
N := Build2_Uresize
- (Build_Context, N, Dtype.W, Get_Location (Loc));
+ (Ctxt, N, Dtype.W, Get_Location (Loc));
end if;
return Create_Value_Net (N, Dtype);
when Value_Const =>
return Synth_Subtype_Conversion
- ((Vt.Typ, Vt.Val.C_Val), Dtype, Bounds, Loc);
+ (Ctxt, (Vt.Typ, Vt.Val.C_Val), Dtype, Bounds, Loc);
when Value_Memory =>
return Create_Value_Discrete
(Read_Discrete (Vt), Dtype);
@@ -1053,7 +1053,8 @@ package body Synth.Expr is
end Index_To_Offset;
function Dyn_Index_To_Offset
- (Bnd : Bound_Type; Idx_Val : Valtyp; Loc : Node) return Net
+ (Ctxt : Context_Acc; Bnd : Bound_Type; Idx_Val : Valtyp; Loc : Node)
+ return Net
is
Idx2 : Net;
Off : Net;
@@ -1061,24 +1062,23 @@ package body Synth.Expr is
Wbounds : Width;
begin
Wbounds := Clog2 (Bnd.Len);
- Idx2 := Synth_Resize (Idx_Val, Wbounds, Loc);
+ Idx2 := Synth_Resize (Ctxt, Idx_Val, Wbounds, Loc);
if Bnd.Right = 0 and then Bnd.Dir = Dir_Downto then
-- Simple case without adjustments.
return Idx2;
end if;
- Right := Build_Const_UB32 (Build_Context, To_Uns32 (Bnd.Right),
- Wbounds);
+ Right := Build_Const_UB32 (Ctxt, To_Uns32 (Bnd.Right), Wbounds);
Set_Location (Right, Loc);
case Bnd.Dir is
when Dir_To =>
-- L <= I <= R --> off = R - I
- Off := Build_Dyadic (Build_Context, Id_Sub, Right, Idx2);
+ Off := Build_Dyadic (Ctxt, Id_Sub, Right, Idx2);
when Dir_Downto =>
-- L >= I >= R --> off = I - R
- Off := Build_Dyadic (Build_Context, Id_Sub, Idx2, Right);
+ Off := Build_Dyadic (Ctxt, Id_Sub, Idx2, Right);
end case;
Set_Location (Off, Loc);
return Off;
@@ -1135,6 +1135,7 @@ package body Synth.Expr is
Voff : out Net;
Off : out Value_Offsets)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Indexes : constant Iir_Flist := Get_Index_List (Name);
El_Typ : constant Type_Acc := Get_Array_Element (Pfx_Type);
Idx_Expr : Node;
@@ -1170,7 +1171,7 @@ package body Synth.Expr is
Off.Mem_Off := Off.Mem_Off
+ Idx_Off.Mem_Off * Size_Type (Stride) * El_Typ.Sz;
else
- Ivoff := Dyn_Index_To_Offset (Bnd, Idx_Val, Name);
+ Ivoff := Dyn_Index_To_Offset (Ctxt, Bnd, Idx_Val, Name);
Ivoff := Build_Memidx
(Get_Build (Syn_Inst), Ivoff, El_Typ.W * Stride,
Bnd.Len - 1,
@@ -1408,6 +1409,7 @@ package body Synth.Expr is
Inp : out Net;
Off : out Value_Offsets)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Expr : constant Node := Get_Suffix (Name);
Left, Right : Valtyp;
Dir : Direction_Type;
@@ -1470,9 +1472,8 @@ package body Synth.Expr is
end if;
Synth_Extract_Dyn_Suffix
- (Get_Build (Syn_Inst), Name,
- Pfx_Bnd, Get_Net (Left), Get_Net (Right), Inp, Step, Off.Net_Off,
- Res_Bnd.Len);
+ (Ctxt, Name, Pfx_Bnd, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right),
+ Inp, Step, Off.Net_Off, Res_Bnd.Len);
if Inp = No_Net then
return;
end if;
@@ -1489,8 +1490,7 @@ package body Synth.Expr is
Max := 2**Natural (Inp_W) - 1;
end if;
Inp := Build_Memidx
- (Get_Build (Syn_Inst),
- Inp, Step * El_Typ.W, Max,
+ (Ctxt, Inp, Step * El_Typ.W, Max,
Inp_W + Width (Clog2 (Uns64 (Step * El_Typ.W))));
end if;
end Synth_Slice_Suffix;
@@ -1531,7 +1531,7 @@ package body Synth.Expr is
Posedge : Boolean;
Res : Net;
begin
- Clk := Get_Net (Synth_Name (Syn_Inst, Prefix));
+ Clk := Get_Net (Ctxt, Synth_Name (Syn_Inst, Prefix));
if Get_Kind (Expr) /= Iir_Kind_Equality_Operator then
Error_Msg_Synth (+Expr, "ill-formed clock-level, '=' expected");
Res := Build_Posedge (Ctxt, Clk);
@@ -1750,6 +1750,7 @@ package body Synth.Expr is
Expr : Node;
En : Net) return Valtyp
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Left : Valtyp;
Right : Valtyp;
Val : Int64;
@@ -1787,7 +1788,8 @@ package body Synth.Expr is
return Create_Value_Discrete (Val, Boolean_Type);
end if;
- N := Build_Dyadic (Build_Context, Id, Get_Net (Left), Get_Net (Right));
+ N := Build_Dyadic (Ctxt, Id,
+ Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Boolean_Type);
end Synth_Short_Circuit;
@@ -1894,6 +1896,7 @@ package body Synth.Expr is
end;
when Iir_Kind_Selected_Element =>
declare
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Idx : constant Iir_Index32 :=
Get_Element_Position (Get_Named_Entity (Expr));
Pfx : constant Node := Get_Prefix (Expr);
@@ -1913,7 +1916,7 @@ package body Synth.Expr is
return Res;
else
N := Build_Extract
- (Build_Context, Get_Net (Val),
+ (Ctxt, Get_Net (Ctxt, Val),
Val.Typ.Rec.E (Idx + 1).Boff, Get_Type_Width (Res_Typ));
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Typ);
@@ -2020,6 +2023,7 @@ package body Synth.Expr is
when Iir_Kind_Pos_Attribute
| Iir_Kind_Val_Attribute =>
declare
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Param : constant Node := Get_Parameter (Expr);
V : Valtyp;
Dtype : Type_Acc;
@@ -2028,7 +2032,7 @@ package body Synth.Expr is
Dtype := Get_Subtype_Object (Syn_Inst, Get_Type (Expr));
-- FIXME: to be generalized. Not always as simple as a
-- subtype conversion.
- return Synth_Subtype_Conversion (V, Dtype, False, Expr);
+ return Synth_Subtype_Conversion (Ctxt, V, Dtype, False, Expr);
end;
when Iir_Kind_Low_Type_Attribute =>
return Synth_Low_High_Type_Attribute (Syn_Inst, Expr, Dir_To);
diff --git a/src/synth/synth-expr.ads b/src/synth/synth-expr.ads
index 5104bcaaf..73287b49e 100644
--- a/src/synth/synth-expr.ads
+++ b/src/synth/synth-expr.ads
@@ -23,6 +23,7 @@ with Ada.Unchecked_Deallocation;
with Types; use Types;
with Netlists; use Netlists;
+with Netlists.Builders; use Netlists.Builders;
with Synth.Source;
with Synth.Objtypes; use Synth.Objtypes;
@@ -32,7 +33,8 @@ with Vhdl.Nodes; use Vhdl.Nodes;
package Synth.Expr is
-- Perform a subtype conversion. Check constraints.
- function Synth_Subtype_Conversion (Vt : Valtyp;
+ function Synth_Subtype_Conversion (Ctxt : Context_Acc;
+ Vt : Valtyp;
Dtype : Type_Acc;
Bounds : Boolean;
Loc : Source.Syn_Src)
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index 2f674883d..572ccf5ac 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -632,6 +632,7 @@ package body Synth.Insts is
return Net
is
use Netlists.Concats;
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Iassoc : Node;
V : Valtyp;
Off : Uns32;
@@ -673,12 +674,12 @@ package body Synth.Insts is
pragma Assert (N_Off = Els.Table (I).Off);
V := Els.Table (I).Val;
N_Off := N_Off + V.Typ.W;
- Append (Concat, Get_Net (V));
+ Append (Concat, Get_Net (Ctxt, V));
end loop;
Value_Offset_Tables.Free (Els);
-- 3. connect
- Build (Get_Build (Syn_Inst), Concat, N);
+ Build (Ctxt, Concat, N);
return N;
end Synth_Individual_Input_Assoc;
@@ -688,6 +689,7 @@ package body Synth.Insts is
Inter : Node)
return Net
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Actual : Node;
Formal_Typ : Type_Acc;
Act_Inst : Synth_Instance_Acc;
@@ -716,7 +718,7 @@ package body Synth.Insts is
Act := Synth_Expression_With_Type
(Act_Inst, Actual, Formal_Typ, No_Net);
- return Get_Net (Act);
+ return Get_Net (Ctxt, Act);
end Synth_Input_Assoc;
procedure Synth_Individual_Output_Assoc (Outp : Net;
@@ -1049,6 +1051,7 @@ package body Synth.Insts is
procedure Synth_Component_Instantiation_Statement
(Syn_Inst : Synth_Instance_Acc; Stmt : Node)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Component : constant Node :=
Get_Named_Entity (Get_Instantiated_Unit (Stmt));
Config : constant Node := Get_Component_Configuration (Stmt);
@@ -1190,7 +1193,7 @@ package body Synth.Insts is
if Mode_To_Port_Kind (Get_Mode (Inter)) = Port_Out then
O := Get_Value (Comp_Inst, Inter);
- Port := Get_Net (O);
+ Port := Get_Net (Ctxt, O);
Synth_Output_Assoc (Port, Syn_Inst, Assoc, Comp_Inst, Inter);
Nbr_Outputs := Nbr_Outputs + 1;
end if;
@@ -1352,6 +1355,7 @@ package body Synth.Insts is
Idx : Port_Idx;
Val : Valtyp)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Default : constant Node := Get_Default_Value (Inter);
Desc : constant Port_Desc :=
Get_Output_Desc (Get_Module (Self_Inst), Idx);
@@ -1388,10 +1392,10 @@ package body Synth.Insts is
Init := Synth_Expression_With_Type
(Syn_Inst, Default, Inter_Typ, No_Net);
Init := Synth_Subtype_Conversion
- (Init, Inter_Typ, False, Inter);
- Value := Builders.Build_Ioutput (Build_Context, Get_Net (Init));
+ (Ctxt, Init, Inter_Typ, False, Inter);
+ Value := Builders.Build_Ioutput (Ctxt, Get_Net (Ctxt, Init));
else
- Value := Builders.Build_Output (Build_Context, Desc.W);
+ Value := Builders.Build_Output (Ctxt, Desc.W);
end if;
Connect (Inp, Value);
end if;
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb
index 2dc5a10aa..7944ba3b2 100644
--- a/src/synth/synth-oper.adb
+++ b/src/synth/synth-oper.adb
@@ -48,7 +48,8 @@ package body Synth.Oper is
return Build2_Uresize (Build_Context, N, W, Get_Location (Loc));
end Synth_Uresize;
- function Synth_Uresize (Val : Valtyp; W : Width; Loc : Node) return Net
+ function Synth_Uresize
+ (Ctxt : Context_Acc; Val : Valtyp; W : Width; Loc : Node) return Net
is
Res : Net;
begin
@@ -58,15 +59,16 @@ package body Synth.Oper is
raise Internal_Error;
else
Res := Build2_Const_Uns
- (Build_Context, To_Uns64 (Read_Discrete (Val)), W);
+ (Ctxt, To_Uns64 (Read_Discrete (Val)), W);
end if;
Set_Location (Res, Loc);
return Res;
end if;
- return Synth_Uresize (Get_Net (Val), W, Loc);
+ return Synth_Uresize (Get_Net (Ctxt, Val), W, Loc);
end Synth_Uresize;
- function Synth_Sresize (Val : Valtyp; W : Width; Loc : Node) return Net
+ function Synth_Sresize
+ (Ctxt : Context_Acc; Val : Valtyp; W : Width; Loc : Node) return Net
is
Res : Net;
begin
@@ -80,12 +82,13 @@ package body Synth.Oper is
Set_Location (Res, Loc);
return Res;
end if;
- return Build2_Sresize (Build_Context, Get_Net (Val), W,
+ return Build2_Sresize (Ctxt, Get_Net (Ctxt, Val), W,
Get_Location (Loc));
end Synth_Sresize;
- function Synth_Bit_Eq_Const (Cst : Valtyp; Expr : Valtyp; Loc : Node)
- return Valtyp
+ function Synth_Bit_Eq_Const
+ (Ctxt : Context_Acc; Cst : Valtyp; Expr : Valtyp; Loc : Node)
+ return Valtyp
is
Val : Uns32;
Zx : Uns32;
@@ -100,20 +103,20 @@ package body Synth.Oper is
To_Logic (Read_Discrete (Cst), Cst.Typ, Val, Zx);
if Zx /= 0 then
-- Equal unknown -> return X
- N := Build_Const_UL32 (Build_Context, 0, 1, 1);
+ N := Build_Const_UL32 (Ctxt, 0, 1, 1);
Set_Location (N, Loc);
return Create_Value_Net (N, Boolean_Type);
elsif Val = 1 then
-- The result type is a boolean; convert if needed.
if Expr.Typ.Kind = Type_Logic then
- return Create_Value_Net (Get_Net (Expr), Boolean_Type);
+ return Create_Value_Net (Get_Net (Ctxt, Expr), Boolean_Type);
else
pragma Assert (Expr.Typ.Kind = Type_Bit);
return Expr;
end if;
else
pragma Assert (Val = 0);
- N := Build_Monadic (Build_Context, Id_Not, Get_Net (Expr));
+ N := Build_Monadic (Ctxt, Id_Not, Get_Net (Ctxt, Expr));
Set_Location (N, Loc);
return Create_Value_Net (N, Boolean_Type);
end if;
@@ -184,7 +187,8 @@ package body Synth.Oper is
-- Do a match comparison between CST and OPER.
-- Return No_Net if CST has incorrect value.
- function Synth_Match (Cst : Valtyp;
+ function Synth_Match (Ctxt : Context_Acc;
+ Cst : Valtyp;
Oper : Valtyp;
Expr : Node;
Op : Compare_Module_Id := Id_Eq) return Net
@@ -243,23 +247,25 @@ package body Synth.Oper is
end loop;
-- Generate and + eq
- Nv := Build2_Const_Vec (Build_Context, Wd, Vals.all);
+ Nv := Build2_Const_Vec (Ctxt, Wd, Vals.all);
Set_Location (Nv, Expr);
Unchecked_Deallocate (Vals);
- Nm := Build2_Const_Vec (Build_Context, Wd, Mask.all);
+ Nm := Build2_Const_Vec (Ctxt, Wd, Mask.all);
Set_Location (Nm, Expr);
Unchecked_Deallocate (Mask);
- Res := Build_Dyadic (Build_Context, Id_And, Get_Net (Oper), Nm);
+ Res := Build_Dyadic (Ctxt, Id_And, Get_Net (Ctxt, Oper), Nm);
Set_Location (Res, Expr);
- Res := Build_Compare (Build_Context, Op, Res, Nv);
+ Res := Build_Compare (Ctxt, Op, Res, Nv);
Set_Location (Res, Expr);
return Res;
end Synth_Match;
-- Note: LEFT or RIGHT can be a single bit.
- function Synth_Dyadic_Uns_Uns
- (Id : Dyadic_Module_Id; Left, Right : Valtyp; Expr : Node) return Valtyp
+ function Synth_Dyadic_Uns_Uns (Ctxt : Context_Acc;
+ Id : Dyadic_Module_Id;
+ Left, Right : Valtyp;
+ Expr : Node) return Valtyp
is
W : constant Width := Width'Max (Left.Typ.W, Right.Typ.W);
El_Typ : Type_Acc;
@@ -275,42 +281,48 @@ package body Synth.Oper is
raise Internal_Error;
end if;
Rtype := Create_Vec_Type_By_Length (W, El_Typ);
- L1 := Synth_Uresize (Left, W, Expr);
- R1 := Synth_Uresize (Right, W, Expr);
- N := Build_Dyadic (Build_Context, Id, L1, R1);
+ L1 := Synth_Uresize (Ctxt, Left, W, Expr);
+ R1 := Synth_Uresize (Ctxt, Right, W, Expr);
+ N := Build_Dyadic (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end Synth_Dyadic_Uns_Uns;
- function Synth_Dyadic_Uns_Nat
- (Id : Dyadic_Module_Id; Left, Right : Valtyp; Expr : Node) return Valtyp
+ function Synth_Dyadic_Uns_Nat (Ctxt : Context_Acc;
+ Id : Dyadic_Module_Id;
+ Left, Right : Valtyp;
+ Expr : Node) return Valtyp
is
- L : constant Net := Get_Net (Left);
+ L : constant Net := Get_Net (Ctxt, Left);
R1 : Net;
N : Net;
begin
- R1 := Synth_Uresize (Right, Left.Typ.W, Expr);
- N := Build_Dyadic (Build_Context, Id, L, R1);
+ R1 := Synth_Uresize (Ctxt, Right, Left.Typ.W, Expr);
+ N := Build_Dyadic (Ctxt, Id, L, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Left));
end Synth_Dyadic_Uns_Nat;
- function Synth_Dyadic_Nat_Uns
- (Id : Dyadic_Module_Id; Left, Right : Valtyp; Expr : Node) return Valtyp
+ function Synth_Dyadic_Nat_Uns (Ctxt : Context_Acc;
+ Id : Dyadic_Module_Id;
+ Left, Right : Valtyp;
+ Expr : Node) return Valtyp
is
- R : constant Net := Get_Net (Right);
+ R : constant Net := Get_Net (Ctxt, Right);
L1 : Net;
N : Net;
begin
- L1 := Synth_Uresize (Left, Right.Typ.W, Expr);
- N := Build_Dyadic (Build_Context, Id, L1, R);
+ L1 := Synth_Uresize (Ctxt, Left, Right.Typ.W, Expr);
+ N := Build_Dyadic (Ctxt, Id, L1, R);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Right));
end Synth_Dyadic_Nat_Uns;
-- Note: LEFT or RIGHT can be a single bit.
- function Synth_Dyadic_Sgn_Sgn
- (Id : Dyadic_Module_Id; Left, Right : Valtyp; Expr : Node) return Valtyp
+ function Synth_Dyadic_Sgn_Sgn (Ctxt : Context_Acc;
+ Id : Dyadic_Module_Id;
+ Left, Right : Valtyp;
+ Expr : Node) return Valtyp
is
W : constant Width := Width'Max (Left.Typ.W, Right.Typ.W);
El_Typ : Type_Acc;
@@ -326,35 +338,39 @@ package body Synth.Oper is
raise Internal_Error;
end if;
Rtype := Create_Vec_Type_By_Length (W, El_Typ);
- L1 := Synth_Sresize (Left, W, Expr);
- R1 := Synth_Sresize (Right, W, Expr);
- N := Build_Dyadic (Build_Context, Id, L1, R1);
+ L1 := Synth_Sresize (Ctxt, Left, W, Expr);
+ R1 := Synth_Sresize (Ctxt, Right, W, Expr);
+ N := Build_Dyadic (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end Synth_Dyadic_Sgn_Sgn;
- function Synth_Dyadic_Sgn_Int
- (Id : Dyadic_Module_Id; Left, Right : Valtyp; Expr : Node) return Valtyp
+ function Synth_Dyadic_Sgn_Int (Ctxt : Context_Acc;
+ Id : Dyadic_Module_Id;
+ Left, Right : Valtyp;
+ Expr : Node) return Valtyp
is
- L : constant Net := Get_Net (Left);
+ L : constant Net := Get_Net (Ctxt, Left);
R1 : Net;
N : Net;
begin
- R1 := Synth_Sresize (Right, Left.Typ.W, Expr);
- N := Build_Dyadic (Build_Context, Id, L, R1);
+ R1 := Synth_Sresize (Ctxt, Right, Left.Typ.W, Expr);
+ N := Build_Dyadic (Ctxt, Id, L, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Left));
end Synth_Dyadic_Sgn_Int;
- function Synth_Dyadic_Int_Sgn
- (Id : Dyadic_Module_Id; Left, Right : Valtyp; Expr : Node) return Valtyp
+ function Synth_Dyadic_Int_Sgn (Ctxt : Context_Acc;
+ Id : Dyadic_Module_Id;
+ Left, Right : Valtyp;
+ Expr : Node) return Valtyp
is
- R : constant Net := Get_Net (Right);
+ R : constant Net := Get_Net (Ctxt, Right);
L1 : Net;
N : Net;
begin
- L1 := Synth_Sresize (Left, Right.Typ.W, Expr);
- N := Build_Dyadic (Build_Context, Id, R, L1);
+ L1 := Synth_Sresize (Ctxt, Left, Right.Typ.W, Expr);
+ N := Build_Dyadic (Ctxt, Id, R, L1);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Right));
end Synth_Dyadic_Int_Sgn;
@@ -387,8 +403,8 @@ package body Synth.Oper is
is
N : Net;
begin
- N := Build_Dyadic (Build_Context, Id,
- Get_Net (Left), Get_Net (Right));
+ N := Build_Dyadic
+ (Ctxt, Id, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Left.Typ);
end Synth_Bit_Dyadic;
@@ -401,21 +417,21 @@ package body Synth.Oper is
pragma Assert (Left_Type = Right_Type);
pragma Assert (Res_Type = Expr_Typ);
N := Build_Compare
- (Build_Context, Id, Get_Net (Left), Get_Net (Right));
+ (Ctxt, Id, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Type);
end Synth_Compare;
function Synth_Minmax (Id : Compare_Module_Id) return Valtyp
is
- L : constant Net := Get_Net (Left);
- R : constant Net := Get_Net (Right);
+ L : constant Net := Get_Net (Ctxt, Left);
+ R : constant Net := Get_Net (Ctxt, Right);
Sel, N : Net;
begin
pragma Assert (Left_Type = Right_Type);
- Sel := Build_Compare (Build_Context, Id, L, R);
+ Sel := Build_Compare (Ctxt, Id, L, R);
Set_Location (Sel, Expr);
- N := Build_Mux2 (Build_Context, Sel, R, L);
+ N := Build_Mux2 (Ctxt, Sel, R, L);
Set_Location (N, Expr);
return Create_Value_Net (N, Expr_Typ);
end Synth_Minmax;
@@ -430,7 +446,7 @@ package body Synth.Oper is
(+Expr, "comparing non-numeric vector is unexpected");
if Left.Typ.W = Right.Typ.W then
N := Build_Compare
- (Get_Build (Syn_Inst), Id, Get_Net (Left), Get_Net (Right));
+ (Ctxt, Id, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Type);
elsif Left.Typ.W < Right.Typ.W then
@@ -450,8 +466,8 @@ package body Synth.Oper is
is
N : Net;
begin
- N := Synth_Uresize (Right, Left.Typ.W, Expr);
- N := Build_Compare (Build_Context, Id, Get_Net (Left), N);
+ N := Synth_Uresize (Ctxt, Right, Left.Typ.W, Expr);
+ N := Build_Compare (Ctxt, Id, Get_Net (Ctxt, Left), N);
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Type);
end Synth_Compare_Uns_Nat;
@@ -461,8 +477,8 @@ package body Synth.Oper is
is
N : Net;
begin
- N := Synth_Uresize (Left, Right.Typ.W, Expr);
- N := Build_Compare (Build_Context, Id, Get_Net (Right), N);
+ N := Synth_Uresize (Ctxt, Left, Right.Typ.W, Expr);
+ N := Build_Compare (Ctxt, Id, Get_Net (Ctxt, Right), N);
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Type);
end Synth_Compare_Nat_Uns;
@@ -472,8 +488,8 @@ package body Synth.Oper is
is
N : Net;
begin
- N := Synth_Sresize (Right, Left.Typ.W, Expr);
- N := Build_Compare (Build_Context, Id, Get_Net (Left), N);
+ N := Synth_Sresize (Ctxt, Right, Left.Typ.W, Expr);
+ N := Build_Compare (Ctxt, Id, Get_Net (Ctxt, Left), N);
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Typ);
end Synth_Compare_Sgn_Int;
@@ -483,8 +499,8 @@ package body Synth.Oper is
is
N : Net;
begin
- N := Synth_Sresize (Left, Right.Typ.W, Expr);
- N := Build_Compare (Build_Context, Id, N, Get_Net (Right));
+ N := Synth_Sresize (Ctxt, Left, Right.Typ.W, Expr);
+ N := Build_Compare (Ctxt, Id, N, Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Typ);
end Synth_Compare_Int_Sgn;
@@ -497,8 +513,8 @@ package body Synth.Oper is
Error_Msg_Synth (+Expr, "operands don't have the same length");
return No_Valtyp;
end if;
- N := Build_Dyadic (Build_Context, Id,
- Get_Net (Left), Get_Net (Right));
+ N := Build_Dyadic (Ctxt, Id,
+ Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Left));
end Synth_Vec_Dyadic;
@@ -509,7 +525,7 @@ package body Synth.Oper is
N : Net;
begin
N := Build_Dyadic
- (Build_Context, Id, Get_Net (Left), Get_Net (Right));
+ (Ctxt, Id, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Etype);
end Synth_Int_Dyadic;
@@ -521,9 +537,9 @@ package body Synth.Oper is
L1, R1 : Net;
N : Net;
begin
- L1 := Synth_Uresize (Left, W, Expr);
- R1 := Synth_Uresize (Right, W, Expr);
- N := Build_Compare (Build_Context, Id, L1, R1);
+ L1 := Synth_Uresize (Ctxt, Left, W, Expr);
+ R1 := Synth_Uresize (Ctxt, Right, W, Expr);
+ N := Build_Compare (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Type);
end Synth_Compare_Uns_Uns;
@@ -535,9 +551,9 @@ package body Synth.Oper is
L1, R1 : Net;
N : Net;
begin
- L1 := Synth_Sresize (Left, W, Expr);
- R1 := Synth_Sresize (Right, W, Expr);
- N := Build_Compare (Build_Context, Id, L1, R1);
+ L1 := Synth_Sresize (Ctxt, Left, W, Expr);
+ R1 := Synth_Sresize (Ctxt, Right, W, Expr);
+ N := Build_Compare (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Typ);
end Synth_Compare_Sgn_Sgn;
@@ -552,8 +568,8 @@ package body Synth.Oper is
Res_Typ : Type_Acc;
N : Net;
begin
- L1 := Synth_Uresize (Left, W, Expr);
- R1 := Synth_Uresize (Right, W, Expr);
+ L1 := Synth_Uresize (Ctxt, Left, W, Expr);
+ R1 := Synth_Uresize (Ctxt, Right, W, Expr);
case Vec is
when Oper_Left =>
Res_Typ := Left.Typ;
@@ -575,8 +591,8 @@ package body Synth.Oper is
Res_Typ : Type_Acc;
N : Net;
begin
- L1 := Synth_Sresize (Left, W, Expr);
- R1 := Synth_Sresize (Right, W, Expr);
+ L1 := Synth_Sresize (Ctxt, Left, W, Expr);
+ R1 := Synth_Sresize (Ctxt, Right, W, Expr);
case Vec is
when Oper_Left =>
Res_Typ := Left.Typ;
@@ -596,8 +612,8 @@ package body Synth.Oper is
L1, R1 : Net;
N, Nn, Nr1, Cond : Net;
begin
- L1 := Get_Net (Left);
- R1 := Get_Net (Right);
+ L1 := Get_Net (Ctxt, Left);
+ R1 := Get_Net (Ctxt, Right);
-- Handle the case when the RHS is positive.
N := Build_Shift_Rotate (Ctxt, Sh_Pos, L1, R1);
@@ -642,7 +658,7 @@ package body Synth.Oper is
Error_Msg_Synth (+Expr, "rotation quantity must be unsigned");
return Left;
else
- R1 := Get_Net (Right);
+ R1 := Get_Net (Ctxt, Right);
Ww := Netlists.Utils.Clog2 (Left.Typ.W);
if Right.Typ.W >= Ww then
if Mutils.Is_Power2 (Uns64 (Left.Typ.W)) then
@@ -654,7 +670,7 @@ package body Synth.Oper is
end if;
end if;
end if;
- L1 := Get_Net (Left);
+ L1 := Get_Net (Ctxt, Left);
N := Build_Shift_Rotate (Ctxt, Id, L1, R1);
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Left));
@@ -665,13 +681,13 @@ package body Synth.Oper is
if Left = No_Valtyp then
return No_Valtyp;
end if;
- Left := Synth_Subtype_Conversion (Left, Left_Typ, False, Expr);
+ Left := Synth_Subtype_Conversion (Ctxt, Left, Left_Typ, False, Expr);
Right := Synth_Expression_With_Type
(Syn_Inst, Right_Expr, Right_Typ, En);
if Right = No_Valtyp then
return No_Valtyp;
end if;
- Right := Synth_Subtype_Conversion (Right, Right_Typ, False, Expr);
+ Right := Synth_Subtype_Conversion (Ctxt, Right, Right_Typ, False, Expr);
if Is_Static_Val (Left.Val) and Is_Static_Val (Right.Val) then
Srec := Synth_Static_Dyadic_Predefined
@@ -745,9 +761,9 @@ package body Synth.Oper is
or else Left_Typ = Logic_Type
then
if Is_Static (Left.Val) then
- return Synth_Bit_Eq_Const (Left, Right, Expr);
+ return Synth_Bit_Eq_Const (Ctxt, Left, Right, Expr);
elsif Is_Static (Right.Val) then
- return Synth_Bit_Eq_Const (Right, Left, Expr);
+ return Synth_Bit_Eq_Const (Ctxt, Right, Left, Expr);
end if;
end if;
return Synth_Compare (Id_Eq, Boolean_Type);
@@ -801,7 +817,7 @@ package body Synth.Oper is
(+Expr, "no operand of ?= is constant, handled like =");
return Synth_Compare (Id_Eq, Logic_Type);
end if;
- Res := Synth_Match (Cst, Oper, Expr);
+ Res := Synth_Match (Ctxt, Cst, Oper, Expr);
if Res = No_Net then
return Create_Value_Discrete (Std_Logic_X_Pos, Expr_Typ);
else
@@ -830,7 +846,7 @@ package body Synth.Oper is
(+Expr, "no operand of ?/= is constant, handled like /=");
return Synth_Compare (Id_Ne, Logic_Type);
end if;
- Res := Synth_Match (Cst, Oper, Expr, Id_Ne);
+ Res := Synth_Match (Ctxt, Cst, Oper, Expr, Id_Ne);
if Res = No_Net then
return Create_Value_Discrete (Std_Logic_X_Pos, Expr_Typ);
else
@@ -856,10 +872,10 @@ package body Synth.Oper is
when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int =>
-- "+" (Unsigned, Natural)
- return Synth_Dyadic_Uns_Nat (Id_Add, Left, Right, Expr);
+ return Synth_Dyadic_Uns_Nat (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns =>
-- "+" (Natural, Unsigned)
- return Synth_Dyadic_Nat_Uns (Id_Add, Left, Right, Expr);
+ return Synth_Dyadic_Nat_Uns (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns
| Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log
@@ -869,16 +885,16 @@ package body Synth.Oper is
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns =>
-- "+" (Unsigned, Unsigned)
- return Synth_Dyadic_Uns_Uns (Id_Add, Left, Right, Expr);
+ return Synth_Dyadic_Uns_Uns (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int
| Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int =>
-- "+" (Signed, Integer)
- return Synth_Dyadic_Sgn_Int (Id_Add, Left, Right, Expr);
+ return Synth_Dyadic_Sgn_Int (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv =>
-- "+" (Integer, Signed)
- return Synth_Dyadic_Int_Sgn (Id_Add, Left, Right, Expr);
+ return Synth_Dyadic_Int_Sgn (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log
| Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn
@@ -888,12 +904,12 @@ package body Synth.Oper is
| Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv
| Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv =>
-- "+" (Signed, Signed)
- return Synth_Dyadic_Sgn_Sgn (Id_Add, Left, Right, Expr);
+ return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Add, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int =>
-- "-" (Unsigned, Natural)
- return Synth_Dyadic_Uns_Nat (Id_Sub, Left, Right, Expr);
+ return Synth_Dyadic_Uns_Nat (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv
@@ -902,23 +918,23 @@ package body Synth.Oper is
| Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv
| Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns =>
-- "-" (Unsigned, Unsigned)
- return Synth_Dyadic_Uns_Uns (Id_Sub, Left, Right, Expr);
+ return Synth_Dyadic_Uns_Uns (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns =>
-- "-" (Natural, Unsigned)
- return Synth_Dyadic_Nat_Uns (Id_Sub, Left, Right, Expr);
+ return Synth_Dyadic_Nat_Uns (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int
| Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int =>
-- "-" (Signed, Integer)
- return Synth_Dyadic_Sgn_Int (Id_Sub, Left, Right, Expr);
+ return Synth_Dyadic_Sgn_Int (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn =>
-- "-" (Integer, Signed)
- return Synth_Dyadic_Int_Sgn (Id_Sub, Left, Right, Expr);
+ return Synth_Dyadic_Int_Sgn (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn
| Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log
| Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn
| Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv =>
-- "-" (Signed, Signed)
- return Synth_Dyadic_Sgn_Sgn (Id_Sub, Left, Right, Expr);
+ return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Sub, Left, Right, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Sgn
| Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn
@@ -930,9 +946,9 @@ package body Synth.Oper is
L, R : Net;
N : Net;
begin
- L := Synth_Sresize (Left, W, Left_Expr);
- R := Synth_Sresize (Right, W, Right_Expr);
- N := Build_Dyadic (Build_Context, Id_Smul, L, R);
+ L := Synth_Sresize (Ctxt, Left, W, Left_Expr);
+ R := Synth_Sresize (Ctxt, Right, W, Right_Expr);
+ N := Build_Dyadic (Ctxt, Id_Smul, L, R);
Set_Location (N, Expr);
return Create_Value_Net
(N, Create_Vec_Type_By_Length (W, Left.Typ.Vec_El));
@@ -945,10 +961,10 @@ package body Synth.Oper is
L, R : Net;
N : Net;
begin
- L := Synth_Sresize (Left, W, Left_Expr);
- R := Synth_Sresize (Right, W, Right_Expr);
+ L := Synth_Sresize (Ctxt, Left, W, Left_Expr);
+ R := Synth_Sresize (Ctxt, Right, W, Right_Expr);
Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
- N := Build_Dyadic (Build_Context, Id_Smul, L, R);
+ N := Build_Dyadic (Ctxt, Id_Smul, L, R);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end;
@@ -960,10 +976,10 @@ package body Synth.Oper is
L, R : Net;
N : Net;
begin
- L := Synth_Sresize (Left, W, Left_Expr);
- R := Synth_Sresize (Right, W, Right_Expr);
+ L := Synth_Sresize (Ctxt, Left, W, Left_Expr);
+ R := Synth_Sresize (Ctxt, Right, W, Right_Expr);
Rtype := Create_Vec_Type_By_Length (W, Right.Typ.Vec_El);
- N := Build_Dyadic (Build_Context, Id_Smul, L, R);
+ N := Build_Dyadic (Ctxt, Id_Smul, L, R);
Set_Location (N, Expr);
return Create_Value_Net (N, Rtype);
end;
@@ -978,8 +994,8 @@ package body Synth.Oper is
L, R : Net;
N : Net;
begin
- L := Synth_Uresize (Left, W, Left_Expr);
- R := Synth_Uresize (Right, W, Right_Expr);
+ L := Synth_Uresize (Ctxt, Left, W, Left_Expr);
+ R := Synth_Uresize (Ctxt, Right, W, Right_Expr);
Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
N := Build_Dyadic (Build_Context, Id_Umul, L, R);
Set_Location (N, Expr);
@@ -993,8 +1009,8 @@ package body Synth.Oper is
Rtype : Type_Acc;
N : Net;
begin
- L1 := Synth_Uresize (Left, W, Expr);
- R1 := Synth_Uresize (Right, W, Expr);
+ L1 := Synth_Uresize (Ctxt, Left, W, Expr);
+ R1 := Synth_Uresize (Ctxt, Right, W, Expr);
Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id_Umul, L1, R1);
Set_Location (N, Expr);
@@ -1008,8 +1024,8 @@ package body Synth.Oper is
Rtype : Type_Acc;
N : Net;
begin
- L1 := Synth_Uresize (Left, W, Expr);
- R1 := Synth_Uresize (Right, W, Expr);
+ L1 := Synth_Uresize (Ctxt, Left, W, Expr);
+ R1 := Synth_Uresize (Ctxt, Right, W, Expr);
Rtype := Create_Vec_Type_By_Length (W, Right.Typ.Vec_El);
N := Build_Dyadic (Ctxt, Id_Umul, L1, R1);
Set_Location (N, Expr);
@@ -1023,8 +1039,8 @@ package body Synth.Oper is
L, R : Net;
N : Net;
begin
- L := Synth_Uresize (Left, W, Left_Expr);
- R := Synth_Sresize (Right, W, Right_Expr);
+ L := Synth_Uresize (Ctxt, Left, W, Left_Expr);
+ R := Synth_Sresize (Ctxt, Right, W, Right_Expr);
Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
N := Build_Dyadic (Build_Context, Id_Smul, L, R);
Set_Location (N, Expr);
@@ -1237,11 +1253,11 @@ package body Synth.Oper is
when Iir_Predefined_Array_Element_Concat =>
declare
- L : constant Net := Get_Net (Left);
+ L : constant Net := Get_Net (Ctxt, Left);
Bnd : Bound_Type;
N : Net;
begin
- N := Build_Concat2 (Build_Context, L, Get_Net (Right));
+ N := Build_Concat2 (Ctxt, L, Get_Net (Ctxt, Right));
Set_Location (N, Expr);
Bnd := Create_Bounds_From_Length
(Syn_Inst,
@@ -1253,11 +1269,11 @@ package body Synth.Oper is
end;
when Iir_Predefined_Element_Array_Concat =>
declare
- R : constant Net := Get_Net (Right);
+ R : constant Net := Get_Net (Ctxt, Right);
Bnd : Bound_Type;
N : Net;
begin
- N := Build_Concat2 (Build_Context, Get_Net (Left), R);
+ N := Build_Concat2 (Ctxt, Get_Net (Ctxt, Left), R);
Set_Location (N, Expr);
Bnd := Create_Bounds_From_Length
(Syn_Inst,
@@ -1273,7 +1289,7 @@ package body Synth.Oper is
Bnd : Bound_Type;
begin
N := Build_Concat2
- (Build_Context, Get_Net (Left), Get_Net (Right));
+ (Ctxt, Get_Net (Ctxt, Left), Get_Net (Ctxt, Right));
Set_Location (N, Expr);
Bnd := Create_Bounds_From_Length
(Syn_Inst, Get_Index_Type (Get_Type (Expr), 0), 2);
@@ -1282,8 +1298,8 @@ package body Synth.Oper is
end;
when Iir_Predefined_Array_Array_Concat =>
declare
- L : constant Net := Get_Net (Left);
- R : constant Net := Get_Net (Right);
+ L : constant Net := Get_Net (Ctxt, Left);
+ R : constant Net := Get_Net (Ctxt, Right);
Bnd : Bound_Type;
N : Net;
begin
@@ -1320,7 +1336,7 @@ package body Synth.Oper is
if R > 0 and then Is_Power2 (Uns64 (R)) then
Log_R := Clog2 (Uns64 (R));
pragma Assert (Log_R <= Natural (Left.Typ.W));
- N := Get_Net (Left);
+ N := Get_Net (Ctxt, Left);
N := Build2_Extract (Ctxt, N, 0, Width (Log_R));
N := Build2_Uresize (Ctxt, N, Left.Typ.W,
Get_Location (Expr));
@@ -1386,6 +1402,7 @@ package body Synth.Oper is
Loc : Node;
En : Net) return Valtyp
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Def : constant Iir_Predefined_Functions :=
Get_Implicit_Definition (Imp);
Inter_Chain : constant Node :=
@@ -1398,27 +1415,27 @@ package body Synth.Oper is
is
N : Net;
begin
- N := Build_Monadic (Build_Context, Id, Get_Net (Operand));
+ N := Build_Monadic (Ctxt, Id, Get_Net (Ctxt, Operand));
Set_Location (N, Loc);
return Create_Value_Net (N, Operand.Typ);
end Synth_Bit_Monadic;
function Synth_Vec_Monadic (Id : Monadic_Module_Id) return Valtyp
is
- Op: constant Net := Get_Net (Operand);
+ Op: constant Net := Get_Net (Ctxt, Operand);
N : Net;
begin
- N := Build_Monadic (Build_Context, Id, Op);
+ N := Build_Monadic (Ctxt, Id, Op);
Set_Location (N, Loc);
return Create_Value_Net (N, Create_Res_Bound (Operand));
end Synth_Vec_Monadic;
function Synth_Vec_Reduce_Monadic (Id : Reduce_Module_Id) return Valtyp
is
- Op: constant Net := Get_Net (Operand);
+ Op: constant Net := Get_Net (Ctxt, Operand);
N : Net;
begin
- N := Build_Reduce (Build_Context, Id, Op);
+ N := Build_Reduce (Ctxt, Id, Op);
Set_Location (N, Loc);
return Create_Value_Net (N, Operand.Typ.Vec_El);
end Synth_Vec_Reduce_Monadic;
@@ -1428,7 +1445,8 @@ package body Synth.Oper is
if Operand = No_Valtyp then
return No_Valtyp;
end if;
- Operand := Synth_Subtype_Conversion (Operand, Oper_Typ, False, Loc);
+ Operand := Synth_Subtype_Conversion
+ (Ctxt, Operand, Oper_Typ, False, Loc);
Strip_Const (Operand);
if Is_Static_Val (Operand.Val) then
@@ -1460,13 +1478,13 @@ package body Synth.Oper is
return Synth_Vec_Reduce_Monadic(Id_Red_Or);
when Iir_Predefined_Ieee_1164_Condition_Operator =>
return Create_Value_Net
- (Get_Net (Operand),
+ (Get_Net (Ctxt, Operand),
Get_Subtype_Object (Syn_Inst, Get_Type (Imp)));
when Iir_Predefined_Integer_Negation =>
declare
N : Net;
begin
- N := Build_Monadic (Build_Context, Id_Neg, Get_Net (Operand));
+ N := Build_Monadic (Ctxt, Id_Neg, Get_Net (Ctxt, Operand));
Set_Location (N, Loc);
return Create_Value_Net (N, Operand.Typ);
end;
@@ -1478,14 +1496,15 @@ package body Synth.Oper is
end case;
end Synth_Monadic_Operation;
- function Synth_Shift_Rotate (Id : Shift_Rotate_Module_Id;
+ function Synth_Shift_Rotate (Ctxt : Context_Acc;
+ Id : Shift_Rotate_Module_Id;
Left, Right : Valtyp;
Expr : Node) return Valtyp
is
- L : constant Net := Get_Net (Left);
+ L : constant Net := Get_Net (Ctxt, Left);
N : Net;
begin
- N := Build_Shift_Rotate (Build_Context, Id, L, Get_Net (Right));
+ N := Build_Shift_Rotate (Ctxt, Id, L, Get_Net (Ctxt, Right));
Set_Location (N, Expr);
return Create_Value_Net (N, Create_Res_Bound (Left));
end Synth_Shift_Rotate;
@@ -1518,7 +1537,7 @@ package body Synth.Oper is
return No_Valtyp;
end if;
Size := Uns32 (Read_Discrete (Size_Vt));
- Arg_Net := Get_Net (Arg);
+ Arg_Net := Get_Net (Ctxt, Arg);
Arg_Net := Build2_Resize (Ctxt, Arg_Net, Size, Is_Signed,
Get_Location (Expr));
return Create_Value_Net
@@ -1548,7 +1567,7 @@ package body Synth.Oper is
declare
Edge : Net;
begin
- Edge := Build_Posedge (Ctxt, Get_Net (L));
+ Edge := Build_Posedge (Ctxt, Get_Net (Ctxt, L));
Set_Location (Edge, Expr);
return Create_Value_Net (Edge, Res_Typ);
end;
@@ -1556,7 +1575,7 @@ package body Synth.Oper is
declare
Edge : Net;
begin
- Edge := Build_Negedge (Ctxt, Get_Net (L));
+ Edge := Build_Negedge (Ctxt, Get_Net (Ctxt, L));
Set_Location (Edge, Expr);
return Create_Value_Net (Edge, Res_Typ);
end;
@@ -1572,9 +1591,9 @@ package body Synth.Oper is
if Is_Static (L.Val) then
raise Internal_Error;
end if;
- return Create_Value_Net (Get_Net (L), Create_Res_Bound (L));
+ return Create_Value_Net (Get_Net (Ctxt, L), Create_Res_Bound (L));
when Iir_Predefined_Ieee_1164_To_Bit =>
- return Create_Value_Net (Get_Net (L), Res_Typ);
+ return Create_Value_Net (Get_Net (Ctxt, L), Res_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns
| Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int =>
return Synth_Conv_Vector (False);
@@ -1587,11 +1606,11 @@ package body Synth.Oper is
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer =>
-- UNSIGNED to Natural.
return Create_Value_Net
- (Synth_Uresize (Get_Net (L), Res_Typ.W, Expr), Res_Typ);
+ (Synth_Uresize (Get_Net (Ctxt, L), Res_Typ.W, Expr), Res_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Toint_Sgn_Int =>
-- SIGNED to Integer.
return Create_Value_Net
- (Synth_Sresize (L, Res_Typ.W, Expr), Res_Typ);
+ (Synth_Sresize (Ctxt, L, Res_Typ.W, Expr), Res_Typ);
when Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Nat
| Iir_Predefined_Ieee_Std_Logic_Arith_Ext =>
declare
@@ -1603,7 +1622,7 @@ package body Synth.Oper is
end if;
W := Uns32 (Read_Discrete (R));
return Create_Value_Net
- (Synth_Uresize (Get_Net (L), W, Expr),
+ (Synth_Uresize (Get_Net (Ctxt, L), W, Expr),
Create_Vec_Type_By_Length (W, Logic_Type));
end;
when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat
@@ -1617,53 +1636,54 @@ package body Synth.Oper is
end if;
W := Uns32 (Read_Discrete (R));
return Create_Value_Net
- (Build2_Sresize (Ctxt, Get_Net (L), W, Get_Location (Expr)),
+ (Build2_Sresize (Ctxt, Get_Net (Ctxt, L),
+ W, Get_Location (Expr)),
Create_Vec_Type_By_Length (W, Logic_Type));
end;
when Iir_Predefined_Ieee_Numeric_Std_Shl_Uns_Nat
| Iir_Predefined_Ieee_Numeric_Std_Shl_Sgn_Nat =>
- return Synth_Shift_Rotate (Id_Lsl, L, R, Expr);
+ return Synth_Shift_Rotate (Ctxt, Id_Lsl, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Shr_Uns_Nat =>
- return Synth_Shift_Rotate (Id_Lsr, L, R, Expr);
+ return Synth_Shift_Rotate (Ctxt, Id_Lsr, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Shr_Sgn_Nat =>
- return Synth_Shift_Rotate (Id_Asr, L, R, Expr);
+ return Synth_Shift_Rotate (Ctxt, Id_Asr, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Rol_Uns_Nat =>
- return Synth_Shift_Rotate (Id_Rol, L, R, Expr);
+ return Synth_Shift_Rotate (Ctxt, Id_Rol, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Ror_Uns_Nat =>
- return Synth_Shift_Rotate (Id_Ror, L, R, Expr);
+ return Synth_Shift_Rotate (Ctxt, Id_Ror, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Min_Uns_Uns =>
- return Synth_Dyadic_Uns_Uns (Id_Umin, L, R, Expr);
+ return Synth_Dyadic_Uns_Uns (Ctxt, Id_Umin, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Min_Uns_Nat =>
- return Synth_Dyadic_Uns_Nat (Id_Umin, L, R, Expr);
+ return Synth_Dyadic_Uns_Nat (Ctxt, Id_Umin, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Min_Nat_Uns =>
- return Synth_Dyadic_Nat_Uns (Id_Umin, L, R, Expr);
+ return Synth_Dyadic_Nat_Uns (Ctxt, Id_Umin, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Min_Sgn_Sgn =>
- return Synth_Dyadic_Sgn_Sgn (Id_Smin, L, R, Expr);
+ return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Smin, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Min_Sgn_Int =>
- return Synth_Dyadic_Sgn_Int (Id_Smin, L, R, Expr);
+ return Synth_Dyadic_Sgn_Int (Ctxt, Id_Smin, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Min_Int_Sgn =>
- return Synth_Dyadic_Int_Sgn (Id_Smin, L, R, Expr);
+ return Synth_Dyadic_Int_Sgn (Ctxt, Id_Smin, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Max_Uns_Uns =>
- return Synth_Dyadic_Uns_Uns (Id_Umax, L, R, Expr);
+ return Synth_Dyadic_Uns_Uns (Ctxt, Id_Umax, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Max_Uns_Nat =>
- return Synth_Dyadic_Uns_Nat (Id_Umax, L, R, Expr);
+ return Synth_Dyadic_Uns_Nat (Ctxt, Id_Umax, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Max_Nat_Uns =>
- return Synth_Dyadic_Nat_Uns (Id_Umax, L, R, Expr);
+ return Synth_Dyadic_Nat_Uns (Ctxt, Id_Umax, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Max_Sgn_Sgn =>
- return Synth_Dyadic_Sgn_Sgn (Id_Smax, L, R, Expr);
+ return Synth_Dyadic_Sgn_Sgn (Ctxt, Id_Smax, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Max_Sgn_Int =>
- return Synth_Dyadic_Sgn_Int (Id_Smax, L, R, Expr);
+ return Synth_Dyadic_Sgn_Int (Ctxt, Id_Smax, L, R, Expr);
when Iir_Predefined_Ieee_Numeric_Std_Max_Int_Sgn =>
- return Synth_Dyadic_Int_Sgn (Id_Smax, L, R, Expr);
+ return Synth_Dyadic_Int_Sgn (Ctxt, Id_Smax, L, R, Expr);
when Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Slv
| Iir_Predefined_Ieee_Std_Logic_Misc_Or_Reduce_Suv =>
declare
N : Net;
begin
- N := Build_Reduce (Ctxt, Id_Red_Or, Get_Net (L));
+ N := Build_Reduce (Ctxt, Id_Red_Or, Get_Net (Ctxt, L));
Set_Location (N, Expr);
return Create_Value_Net (N, Res_Typ);
end;
@@ -1690,7 +1710,7 @@ package body Synth.Oper is
(+Expr, "operands of std_match don't have the same size");
return Create_Value_Discrete (0, Boolean_Type);
end if;
- Res := Synth_Match (Cst, Oper, Expr);
+ Res := Synth_Match (Ctxt, Cst, Oper, Expr);
if Res = No_Net then
return Create_Value_Discrete (0, Boolean_Type);
else
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 5bc66b9e7..59a2ed0e1 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -355,9 +355,11 @@ package body Synth.Stmts is
-- Extract a part of VAL from a target aggregate at offset OFF (offset
-- in the array).
- function Aggregate_Extract
- (Val : Valtyp; Off : Uns32; Typ : Type_Acc; Loc : Node)
- return Valtyp
+ function Aggregate_Extract (Ctxt : Context_Acc;
+ Val : Valtyp;
+ Off : Uns32;
+ Typ : Type_Acc;
+ Loc : Node) return Valtyp
is
El_Typ : constant Type_Acc := Get_Array_Element (Val.Typ);
begin
@@ -368,7 +370,7 @@ package body Synth.Stmts is
N : Net;
begin
N := Build2_Extract
- (Build_Context, Get_Net (Val), Off * El_Typ.W, Typ.W);
+ (Ctxt, Get_Net (Ctxt, Val), Off * El_Typ.W, Typ.W);
Set_Location (N, Loc);
return Create_Value_Net (N, Typ);
end;
@@ -396,6 +398,7 @@ package body Synth.Stmts is
Loc : Node;
En : Net)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Targ_Bnd : constant Bound_Type := Get_Array_Bound (Target_Typ, 1);
Choice : Node;
Assoc : Node;
@@ -416,7 +419,8 @@ package body Synth.Stmts is
end if;
Synth_Assignment
(Syn_Inst, Targ_Info,
- Aggregate_Extract (Val, Pos, Targ_Info.Targ_Type, Assoc),
+ Aggregate_Extract (Ctxt, Val, Pos,
+ Targ_Info.Targ_Type, Assoc),
Loc, En);
when others =>
Error_Kind ("synth_assignment_aggregate", Choice);
@@ -431,9 +435,10 @@ package body Synth.Stmts is
Loc : Node;
En : Net)
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
V : Valtyp;
begin
- V := Synth_Subtype_Conversion (Val, Target.Targ_Type, False, Loc);
+ V := Synth_Subtype_Conversion (Ctxt, Val, Target.Targ_Type, False, Loc);
pragma Unreferenced (Val);
if V = No_Valtyp then
-- In case of error.
@@ -463,8 +468,8 @@ package body Synth.Stmts is
-- Forget about null wires.
return;
end if;
- Phi_Assign_Net (Get_Build (Syn_Inst), Target.Obj.Val.W,
- Get_Net (V), Target.Off.Net_Off);
+ Phi_Assign_Net (Ctxt, Target.Obj.Val.W,
+ Get_Net (Ctxt, V), Target.Off.Net_Off);
end if;
else
if not Is_Static (V.Val) then
@@ -485,8 +490,8 @@ package body Synth.Stmts is
N := Get_Current_Assign_Value
(Ctxt, Target.Mem_Obj.Val.W,
Target.Mem_Dyn.Pfx_Off.Net_Off, Target.Mem_Dyn.Pfx_Typ.W);
- N := Build_Dyn_Insert
- (Ctxt, N, Get_Net (V), Target.Mem_Dyn.Voff, Target.Mem_Doff);
+ N := Build_Dyn_Insert (Ctxt, N, Get_Net (Ctxt, V),
+ Target.Mem_Dyn.Voff, Target.Mem_Doff);
Set_Location (N, Loc);
Phi_Assign_Net (Ctxt, Target.Mem_Obj.Val.W, N,
Target.Mem_Dyn.Pfx_Off.Net_Off);
@@ -513,9 +518,10 @@ package body Synth.Stmts is
Dyn : Dyn_Name;
Loc : Node) return Valtyp
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
N : Net;
begin
- N := Get_Net (Obj);
+ N := Get_Net (Ctxt, Obj);
if Dyn.Voff /= No_Net then
Synth.Source.Set_Location_Maybe (N, Loc);
pragma Assert (Off = 0 or Dyn.Pfx_Off.Net_Off = 0);
@@ -533,11 +539,12 @@ package body Synth.Stmts is
Targ : Target_Info;
Loc : Node) return Valtyp
is
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
N : Net;
begin
case Targ.Kind is
when Target_Simple =>
- N := Build2_Extract (Get_Build (Syn_Inst), Get_Net (Targ.Obj),
+ N := Build2_Extract (Ctxt, Get_Net (Ctxt, Targ.Obj),
Targ.Off.Net_Off, Targ.Targ_Type.W);
return Create_Value_Net (N, Targ.Targ_Type);
when Target_Aggregate =>
@@ -585,14 +592,14 @@ package body Synth.Stmts is
-- Mark the error, but try to continue.
Set_Error (Syn_Inst);
else
- V := Get_Net (Val);
+ V := Get_Net (Ctxt, Val);
Cond := Get_Condition (Cwf);
if Cond /= Null_Node then
Cond_Val := Synth_Expression (Syn_Inst, Cond, En);
if Cond_Val = No_Valtyp then
Cond_Net := Build_Const_UB32 (Ctxt, 0, 1);
else
- Cond_Net := Get_Net (Cond_Val);
+ Cond_Net := Get_Net (Ctxt, Cond_Val);
end if;
V := Build_Mux2 (Ctxt, Cond_Net, No_Net, V);
@@ -615,7 +622,7 @@ package body Synth.Stmts is
if Get_Driver (Inp) = No_Net then
-- No else.
Val := Synth_Read (Syn_Inst, Targ, Stmt);
- Connect (Inp, Get_Net (Val));
+ Connect (Inp, Get_Net (Ctxt, Val));
end if;
end if;
Val := Create_Value_Net (First, Targ.Targ_Type);
@@ -683,11 +690,11 @@ package body Synth.Stmts is
while Ce /= Null_Node loop
Val := Synth_Expression_With_Type
(C.Inst, Get_Expression (Ce), Targ_Type, En);
- V := Get_Net (Val);
+ V := Get_Net (Ctxt, Val);
Cond := Get_Condition (Ce);
if Cond /= Null_Node then
Cond_Val := Synth_Expression (C.Inst, Cond, En);
- V := Build_Mux2 (Ctxt, Get_Net (Cond_Val), No_Net, V);
+ V := Build_Mux2 (Ctxt, Get_Net (Ctxt, Cond_Val), No_Net, V);
Set_Location (V, Ce);
end if;
@@ -742,7 +749,7 @@ package body Synth.Stmts is
end if;
else
Prev_Cond := C.W_Cond;
- Cond_Net := Get_Net (Cond_Val);
+ Cond_Net := Get_Net (Ctxt, Cond_Val);
-- Set W_Cond (for the 'then' part).
if Prev_Cond = No_Net then
@@ -1032,7 +1039,7 @@ package body Synth.Stmts is
Pasgns := new Seq_Assign_Value_Array (1 .. Int32 (Alts'Last));
Nets := new Net_Array (1 .. Int32 (Alts'Last));
- Sel_Net := Get_Net (Sel);
+ Sel_Net := Get_Net (Ctxt, Sel);
-- For each wire, compute the result.
for I in Wires'Range loop
@@ -1252,6 +1259,7 @@ package body Synth.Stmts is
(Syn_Inst : Synth_Instance_Acc; Stmt : Node; En : Net)
is
use Vhdl.Sem_Expr;
+ Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
Expr : constant Node := Get_Expression (Stmt);
Choices : constant Node := Get_Selected_Waveform_Chain (Stmt);
@@ -1306,7 +1314,7 @@ package body Synth.Stmts is
Alt_Idx := Alt_Idx + 1;
Alts (Alt_Idx).Val := Get_Net
- (Synth_Waveform
+ (Ctxt, Synth_Waveform
(Syn_Inst, Get_Associated_Chain (Choice), Targ_Type, En));
end if;
@@ -1340,7 +1348,7 @@ package body Synth.Stmts is
-- Build mux2/mux4 tree (group by 4)
Case_El := new Case_Element_Array (1 .. Case_Info.Nbr_Choices);
- Sel_Net := Get_Net (Sel);
+ Sel_Net := Get_Net (Ctxt, Sel);
declare
Res : Net;
@@ -1566,6 +1574,7 @@ package body Synth.Stmts is
Infos : out Target_Info_Array)
is
pragma Assert (Infos'First = 1);
+ Ctxt : constant Context_Acc := Get_Build (Caller_Inst);
Inter : Node;
Inter_Type : Type_Acc;
Assoc : Node;
@@ -1648,7 +1657,7 @@ package body Synth.Stmts is
end if;
-- FIXME: conversion only for constants, reshape for all.
- Val := Synth_Subtype_Conversion (Val, Inter_Type, True, Assoc);
+ Val := Synth_Subtype_Conversion (Ctxt, Val, Inter_Type, True, Assoc);
if Get_Instance_Const (Subprg_Inst) and then not Is_Static (Val.Val)
then
@@ -1697,6 +1706,7 @@ package body Synth.Stmts is
procedure Synth_Subprogram_Association_Wires
(Subprg_Inst : Synth_Instance_Acc; Init : Association_Iterator_Init)
is
+ Ctxt : constant Context_Acc := Get_Build (Subprg_Inst);
Inter : Node;
Assoc : Node;
Val : Valtyp;
@@ -1715,7 +1725,7 @@ package body Synth.Stmts is
Val := Get_Value (Subprg_Inst, Inter);
-- Arguments are passed by copy.
Wire := Alloc_Wire (Wire_Variable, Inter);
- Set_Wire_Gate (Wire, Get_Net (Val));
+ Set_Wire_Gate (Wire, Get_Net (Ctxt, Val));
Val := Create_Value_Wire (Wire, Val.Typ);
Create_Object_Force (Subprg_Inst, Inter, No_Valtyp);
@@ -2311,7 +2321,8 @@ package body Synth.Stmts is
Push_Phi;
Pop_Phi (Phi_False);
- Merge_Phis (Ctxt, Get_Net (Cond_Val), Phi_True, Phi_False, Stmt);
+ Merge_Phis (Ctxt,
+ Get_Net (Ctxt, Cond_Val), Phi_True, Phi_False, Stmt);
end if;
end Synth_Dynamic_Exit_Next_Statement;
@@ -2553,6 +2564,7 @@ package body Synth.Stmts is
procedure Synth_Return_Statement (C : in out Seq_Context; Stmt : Node)
is
Is_Dyn : constant Boolean := not Get_Instance_Const (C.Inst);
+ Ctxt : constant Context_Acc := Get_Build (C.Inst);
Val : Valtyp;
Expr : constant Node := Get_Expression (Stmt);
begin
@@ -2565,7 +2577,7 @@ package body Synth.Stmts is
return;
end if;
- Val := Synth_Subtype_Conversion (Val, C.Ret_Typ, True, Stmt);
+ Val := Synth_Subtype_Conversion (Ctxt, Val, C.Ret_Typ, True, Stmt);
if C.Nbr_Ret = 0 then
C.Ret_Value := Val;
@@ -2582,7 +2594,7 @@ package body Synth.Stmts is
end if;
end if;
if Is_Dyn then
- Phi_Assign_Net (Get_Build (C.Inst), C.W_Val, Get_Net (Val), 0);
+ Phi_Assign_Net (Ctxt, C.W_Val, Get_Net (Ctxt, Val), 0);
end if;
end if;
@@ -2699,7 +2711,7 @@ package body Synth.Stmts is
Set_Error (C.Inst);
return;
end if;
- N := Get_Net (Cond);
+ N := Get_Net (Ctxt, Cond);
if En /= No_Net then
-- Build: En -> Cond
N := Build2_Imp (Ctxt, En, N, Loc);
@@ -2854,7 +2866,7 @@ package body Synth.Stmts is
Push_Phi;
Pop_Phi (Phi_False);
- Merge_Phis (Ctxt, Get_Net (Cond_Val), Phi_True, Phi_False, Stmt);
+ Merge_Phis (Ctxt, Get_Net (Ctxt, Cond_Val), Phi_True, Phi_False, Stmt);
end Synth_Process_Sequential_Statements;
procedure Synth_Process_Statement
@@ -2981,7 +2993,7 @@ package body Synth.Stmts is
end if;
return;
end if;
- Inst := Build_Assert (Ctxt, Synth_Label (Stmt), Get_Net (Val));
+ Inst := Build_Assert (Ctxt, Synth_Label (Stmt), Get_Net (Ctxt, Val));
Set_Location (Inst, Get_Location (Stmt));
end Synth_Concurrent_Assertion_Statement;
@@ -3032,7 +3044,7 @@ package body Synth.Stmts is
declare
E : constant Vhdl.Types.Vhdl_Node := Get_HDL_Node (Expr);
begin
- return Get_Net (Synth_Expression (Syn_Inst, E, No_Net));
+ return Get_Net (Ctxt, Synth_Expression (Syn_Inst, E, No_Net));
end;
when N_Not_Bool =>
pragma Assert (Loc /= No_Location);
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 10:44:27 +0000