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author | Tristan Gingold <tgingold@free.fr> | 2020-09-20 08:43:47 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-09-20 08:43:47 +0200 |
commit | 81150cf4c2bda2665a82a4cb98f81a21ecd6d4c6 (patch) | |
tree | 40ab12d705df337076969d81fdf32c4d0b85203c /src/synth | |
parent | 76a3614439971b635828b004c6041f3ffbceb83d (diff) | |
download | ghdl-81150cf4c2bda2665a82a4cb98f81a21ecd6d4c6.tar.gz ghdl-81150cf4c2bda2665a82a4cb98f81a21ecd6d4c6.tar.bz2 ghdl-81150cf4c2bda2665a82a4cb98f81a21ecd6d4c6.zip |
synth-expr: refine is_positive for wires. For #1460
Diffstat (limited to 'src/synth')
-rw-r--r-- | src/synth/synth-expr.adb | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 4d2dc7e95..8d48eb86c 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -107,8 +107,12 @@ package body Synth.Expr is when Value_Net => N := V.Val.N; when Value_Wire => - return Read_Discrete - (Synth.Environment.Get_Static_Wire (V.Val.W)) >= 0; + if Synth.Environment.Is_Static_Wire (V.Val.W) then + return Read_Discrete + (Synth.Environment.Get_Static_Wire (V.Val.W)) >= 0; + else + return False; + end if; when others => raise Internal_Error; end case; |