aboutsummaryrefslogtreecommitdiffstats
path: root/src/synth
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2019-09-20 04:35:25 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-20 04:35:25 +0200
commit92e75480e2e6aa32318b654aeb59315fecf27ea9 (patch)
tree9cf0abfc1f6f4377ea1c988e0692c2811decfd3f /src/synth
parent5f93829b3dc29022590ffcff8e383f8978add90a (diff)
downloadghdl-92e75480e2e6aa32318b654aeb59315fecf27ea9.tar.gz
ghdl-92e75480e2e6aa32318b654aeb59315fecf27ea9.tar.bz2
ghdl-92e75480e2e6aa32318b654aeb59315fecf27ea9.zip
synth-context: get rid off Set_Block_Scope.
Diffstat (limited to 'src/synth')
-rw-r--r--src/synth/synth-context.adb20
-rw-r--r--src/synth/synth-context.ads5
-rw-r--r--src/synth/synth-insts.adb15
-rw-r--r--src/synth/synth-oper.adb3
-rw-r--r--src/synth/synth-stmts.adb12
-rw-r--r--src/synth/synthesis.adb4
6 files changed, 24 insertions, 35 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 822eb06e8..99dd2cce5 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -26,6 +26,7 @@ with Types_Utils; use Types_Utils;
with Name_Table; use Name_Table;
with Vhdl.Errors; use Vhdl.Errors;
+with Vhdl.Utils;
with Netlists.Builders; use Netlists.Builders;
with Netlists.Concats;
@@ -59,16 +60,25 @@ package body Synth.Context is
end Make_Base_Instance;
function Make_Instance (Parent : Synth_Instance_Acc;
- Info : Sim_Info_Acc;
+ Blk : Node;
Name : Sname := No_Sname)
return Synth_Instance_Acc
is
+ Info : constant Sim_Info_Acc := Get_Info (Blk);
+ Scope : Sim_Info_Acc;
Res : Synth_Instance_Acc;
begin
+ if Get_Kind (Blk) = Iir_Kind_Architecture_Body then
+ -- Architectures are extensions of entities.
+ Scope := Get_Info (Vhdl.Utils.Get_Entity (Blk));
+ else
+ Scope := Info;
+ end if;
+
Res := new Synth_Instance_Type'(Max_Objs => Info.Nbr_Objects,
M => No_Module,
Name => Name,
- Block_Scope => Info,
+ Block_Scope => Scope,
Up_Block => Parent,
Elab_Objects => 0,
Objects => (others => null));
@@ -98,12 +108,6 @@ package body Synth.Context is
return Inst.Name;
end Get_Sname;
- procedure Set_Block_Scope
- (Inst : Synth_Instance_Acc; Scope : Sim_Info_Acc) is
- begin
- Inst.Block_Scope := Scope;
- end Set_Block_Scope;
-
function Create_Value_Instance (Inst : Synth_Instance_Acc)
return Value_Acc is
begin
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index a03517b53..390141468 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -43,7 +43,7 @@ package Synth.Context is
-- Create and free the corresponding synth instance.
function Make_Instance (Parent : Synth_Instance_Acc;
- Info : Sim_Info_Acc;
+ Blk : Node;
Name : Sname := No_Sname)
return Synth_Instance_Acc;
procedure Free_Instance (Synth_Inst : in out Synth_Instance_Acc);
@@ -55,9 +55,6 @@ package Synth.Context is
function Get_Module (Inst : Synth_Instance_Acc) return Module;
pragma Inline (Set_Module, Get_Module);
- procedure Set_Block_Scope
- (Inst : Synth_Instance_Acc; Scope : Sim_Info_Acc);
-
procedure Create_Object
(Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc);
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index 12ac37add..522c5d182 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -29,7 +29,6 @@ with Netlists.Builders;
with Netlists.Utils;
with Vhdl.Utils; use Vhdl.Utils;
-with Vhdl.Annotations; use Vhdl.Annotations;
with Vhdl.Errors;
with Synth.Flags;
@@ -174,9 +173,7 @@ package body Synth.Insts is
end if;
-- Create the instance.
- Syn_Inst := Make_Instance (Root_Instance, Get_Info (Imp), No_Sname);
- -- Make the entity reachable.
- Set_Block_Scope (Syn_Inst, Get_Info (Decl));
+ Syn_Inst := Make_Instance (Root_Instance, Imp, No_Sname);
-- Copy values for generics.
Inter := Get_Generic_Chain (Decl);
@@ -336,7 +333,7 @@ package body Synth.Insts is
begin
-- Elaborate generic + map aspect
Sub_Inst := Make_Instance
- (Syn_Inst, Get_Info (Ent), New_Sname_User (Get_Identifier (Ent)));
+ (Syn_Inst, Ent, New_Sname_User (Get_Identifier (Ent)));
Synth_Subprogram_Association (Sub_Inst, Syn_Inst,
Get_Generic_Chain (Ent),
Get_Generic_Map_Aspect_Chain (Stmt));
@@ -463,7 +460,7 @@ package body Synth.Insts is
-- Create the sub-instance for the component
-- Elaborate generic + map aspect
- Comp_Inst := Make_Instance (Syn_Inst, Get_Info (Component),
+ Comp_Inst := Make_Instance (Syn_Inst, Component,
New_Sname_User (Get_Identifier (Component)));
Synth_Subprogram_Association (Comp_Inst, Syn_Inst,
Get_Generic_Chain (Component),
@@ -528,7 +525,7 @@ package body Synth.Insts is
-- Elaborate generic + map aspect
Sub_Inst := Make_Instance
- (Comp_Inst, Get_Info (Ent), New_Sname_User (Get_Identifier (Ent)));
+ (Comp_Inst, Ent, New_Sname_User (Get_Identifier (Ent)));
Synth_Subprogram_Association (Sub_Inst, Comp_Inst,
Get_Generic_Chain (Ent),
Get_Generic_Map_Aspect_Chain (Bind));
@@ -609,10 +606,8 @@ package body Synth.Insts is
begin
Root_Instance := Global_Instance;
- Syn_Inst := Make_Instance (Global_Instance, Get_Info (Arch),
+ Syn_Inst := Make_Instance (Global_Instance, Arch,
New_Sname_User (Get_Identifier (Entity)));
- -- Make the entity visible.
- Set_Block_Scope (Syn_Inst, Get_Info (Entity));
-- Compute generics.
Inter := Get_Generic_Chain (Entity);
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb
index a6a7883f3..7baa45841 100644
--- a/src/synth/synth-oper.adb
+++ b/src/synth/synth-oper.adb
@@ -28,7 +28,6 @@ with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Utils; use Vhdl.Utils;
with Areapools;
-with Vhdl.Annotations; use Vhdl.Annotations;
with Netlists; use Netlists;
with Netlists.Gates; use Netlists.Gates;
@@ -890,7 +889,7 @@ package body Synth.Oper is
M : Areapools.Mark_Type;
begin
Areapools.Mark (M, Instance_Pool.all);
- Subprg_Inst := Make_Instance (Syn_Inst, Get_Info (Imp));
+ Subprg_Inst := Make_Instance (Syn_Inst, Imp);
Synth_Subprogram_Association
(Subprg_Inst, Syn_Inst, Inter_Chain, Assoc_Chain);
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index b85c77f12..6d023c5e2 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -43,8 +43,6 @@ with Synth.Expr; use Synth.Expr;
with Synth.Insts; use Synth.Insts;
with Synth.Source;
-with Vhdl.Annotations; use Vhdl.Annotations;
-
with Netlists.Builders; use Netlists.Builders;
with Netlists.Gates;
with Netlists.Utils; use Netlists.Utils;
@@ -1226,7 +1224,7 @@ package body Synth.Stmts is
Areapools.Mark (M, Instance_Pool.all);
Sub_Sname := New_Sname (Get_Sname (C.Inst), Get_Identifier (Imp));
- Sub_C.Inst := Make_Instance (C.Inst, Get_Info (Imp), Sub_Sname);
+ Sub_C.Inst := Make_Instance (C.Inst, Imp, Sub_Sname);
Synth_Subprogram_Association
(Sub_C.Inst, C.Inst, Inter_Chain, Assoc_Chain);
@@ -1422,7 +1420,6 @@ package body Synth.Stmts is
is
use Areapools;
Label : constant Name_Id := Get_Identifier (Proc);
- Info : constant Sim_Info_Acc := Get_Info (Proc);
Decls_Chain : constant Node := Get_Declaration_Chain (Proc);
Prev_Instance_Pool : constant Areapool_Acc := Instance_Pool;
M : Areapools.Mark_Type;
@@ -1434,7 +1431,7 @@ package body Synth.Stmts is
else
C_Sname := New_Sname (Get_Sname (Syn_Inst), Label);
end if;
- C := (Inst => Make_Instance (Syn_Inst, Info, C_Sname),
+ C := (Inst => Make_Instance (Syn_Inst, Proc, C_Sname),
T_En => True,
W_En => No_Wire_Id,
W_Ret => No_Wire_Id,
@@ -1497,7 +1494,7 @@ package body Synth.Stmts is
end;
Areapools.Mark (M, Instance_Pool.all);
- C := (Inst => Make_Instance (Syn_Inst, Get_Info (Bod),
+ C := (Inst => Make_Instance (Syn_Inst, Bod,
New_Internal_Name (Build_Context)),
T_En => True,
W_En => No_Wire_Id,
@@ -1823,7 +1820,6 @@ package body Synth.Stmts is
Iterator_Val : Value_Acc := null)
is
use Areapools;
- Info : constant Sim_Info_Acc := Get_Info (Bod);
Decls_Chain : constant Node := Get_Declaration_Chain (Bod);
Prev_Instance_Pool : constant Areapool_Acc := Instance_Pool;
Bod_Inst : Synth_Instance_Acc;
@@ -1831,7 +1827,7 @@ package body Synth.Stmts is
M : Areapools.Mark_Type;
begin
Bod_Sname := New_Sname (Get_Sname (Syn_Inst), Get_Identifier (Bod));
- Bod_Inst := Make_Instance (Syn_Inst, Info, Bod_Sname);
+ Bod_Inst := Make_Instance (Syn_Inst, Bod, Bod_Sname);
-- Same module.
Set_Module (Bod_Inst, Get_Module (Syn_Inst));
Mark (M, Proc_Pool);
diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb
index 7c51e90c8..fadf6e69a 100644
--- a/src/synth/synthesis.adb
+++ b/src/synth/synthesis.adb
@@ -19,7 +19,6 @@
-- MA 02110-1301, USA.
with Vhdl.Utils; use Vhdl.Utils;
-with Vhdl.Annotations; use Vhdl.Annotations;
with Synth.Values; use Synth.Values;
with Synth.Decls; use Synth.Decls;
@@ -50,11 +49,10 @@ package body Synthesis is
is
use Vhdl.Std_Package;
pragma Assert (not Is_Uninstantiated_Package (Pkg));
- Info : constant Sim_Info_Acc := Get_Info (Pkg);
Syn_Inst : Synth_Instance_Acc;
Val : Value_Acc;
begin
- Syn_Inst := Make_Instance (Parent_Inst, Info);
+ Syn_Inst := Make_Instance (Parent_Inst, Pkg);
Val := Create_Value_Instance (Syn_Inst);
if Get_Kind (Get_Parent (Pkg)) = Iir_Kind_Design_Unit then
Create_Package_Object (Parent_Inst, Pkg, Val);