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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-21 16:35:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-21 16:35:48 +0200 |
| commit | 96ee9c9e4cd8b984d6785b06cfdd4cddcd771537 (patch) | |
| tree | f93f00801f4eb639ea07186c8c19c6f14311302e /src/synth | |
| parent | 28e8fd62c58280d96d4733418adc195e6f8db7b0 (diff) | |
| download | ghdl-96ee9c9e4cd8b984d6785b06cfdd4cddcd771537.tar.gz ghdl-96ee9c9e4cd8b984d6785b06cfdd4cddcd771537.tar.bz2 ghdl-96ee9c9e4cd8b984d6785b06cfdd4cddcd771537.zip | |
netlists-disp_vhdl: handle lsr.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index f72defe4f..4681dabec 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -736,6 +736,10 @@ package body Netlists.Disp_Vhdl is Put ((1 .. Natural (Ow - Iw) => '0')); Disp_Template (""" & \i0; -- uext" & NL, Inst); end; + when Id_Lsr => + Disp_Template + (" \o0 <= std_logic_vector " + & "(shift_right (\ui0, to_integer(\ui1)));" & NL, Inst); when Id_Red_Or => declare Iw : constant Width := Get_Width (Get_Input_Net (Inst, 0)); |