simul: complete concurrent procedure calls

2 files changed, 5 insertions, 2 deletions

diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb
index d8c074cd4..7732e47ec 100644
--- a/src/synth/synth-vhdl_decls.adb
+++ b/src/synth/synth-vhdl_decls.adb
@@ -723,8 +723,6 @@ package body Synth.Vhdl_Decls is
             declare
                Val : Valtyp;
             begin
-               pragma Assert (Areapools.Is_Empty (Expr_Pool));
-
                Current_Pool := Instance_Pool;
                Val := Create_Value_Memtyp (Create_Memory_U32 (0));
                Current_Pool := Expr_Pool'Access;
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index b122c11ff..d7a5abbe3 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -3796,6 +3796,11 @@ package body Synth.Vhdl_Stmts is
             when Iir_Kind_Wait_Statement =>
                Error_Msg_Synth
                  (C.Inst, Stmt, "wait statement not allowed for synthesis");
+            when Iir_Kind_Suspend_State_Statement =>
+               --  Could happen in simulation when an 'unknown' procedure
+               --  is called from a sensitized process.
+               --  But this could also be detected during elaboration.
+               null;
             when others =>
                Error_Kind ("synth_sequential_statements", Stmt);
          end case;