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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-22 17:26:53 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-22 17:26:53 +0200 |
| commit | ac8b203059b2d054880550c72adef815ea29950d (patch) | |
| tree | 854e7ba8386880ad3807f9469f27cf967fb27473 /src/synth | |
| parent | 6f9f27d4a643aaae6e5f04bae104f28473c9b695 (diff) | |
| download | ghdl-ac8b203059b2d054880550c72adef815ea29950d.tar.gz ghdl-ac8b203059b2d054880550c72adef815ea29950d.tar.bz2 ghdl-ac8b203059b2d054880550c72adef815ea29950d.zip | |
synth: completly disable inference with -di.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-inference.adb | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb index afb47c965..4ac726c32 100644 --- a/src/synth/synth-inference.adb +++ b/src/synth/synth-inference.adb @@ -463,10 +463,12 @@ package body Synth.Inference is Clk : Net; Enable : Net; begin - Find_Longest_Loop (Val, Prev_Val, Last_Mux, Len); - if Len <= 0 - or else Flags.Flag_Debug_Noinference - then + if not Flags.Flag_Debug_Noinference then + Find_Longest_Loop (Val, Prev_Val, Last_Mux, Len); + else + Len := -1; + end if; + if Len <= 0 then -- No logical loop or self assignment. Add_Conc_Assign (Wid, Val, Off, Stmt); else |