synth: handle static to_bit and to_bitvector. Fix #1540

3 files changed, 60 insertions, 0 deletions

diff --git a/src/synth/synth-ieee-std_logic_1164.adb b/src/synth/synth-ieee-std_logic_1164.adb
index 6aaaa7cdc..b4d103b5b 100644
--- a/src/synth/synth-ieee-std_logic_1164.adb
+++ b/src/synth/synth-ieee-std_logic_1164.adb
@@ -19,6 +19,16 @@
 --  MA 02110-1301, USA.
 
 package body Synth.Ieee.Std_Logic_1164 is
+   function Read_Bit (M : Memory_Ptr; Off : Uns32) return Bit is
+   begin
+      return Bit'Val (Read_U8 (M + Size_Type (Off)));
+   end Read_Bit;
+
+   procedure Write_Bit (M : Memory_Ptr; Off : Uns32; Val : Bit) is
+   begin
+      Write_U8 (M + Size_Type (Off), Bit'Pos (Val));
+   end Write_Bit;
+
    function Read_Std_Logic (M : Memory_Ptr; Off : Uns32) return Std_Ulogic is
    begin
       return Std_Ulogic'Val (Read_U8 (M + Size_Type (Off)));
@@ -29,6 +39,15 @@ package body Synth.Ieee.Std_Logic_1164 is
       Write_U8 (M + Size_Type (Off), Std_Ulogic'Pos (Val));
    end Write_Std_Logic;
 
+   function To_Bit (S : Std_Ulogic; Xmap : Bit) return Bit is
+   begin
+      case S is
+         when '0' | 'L' => return '0';
+         when '1' | 'H' => return '1';
+         when others => return Xmap;
+      end case;
+   end To_Bit;
+
    function Read_Bit_To_Std_Logic (M : Memory_Ptr; Off : Uns32)
                                    return Std_Ulogic is
    begin
diff --git a/src/synth/synth-ieee-std_logic_1164.ads b/src/synth/synth-ieee-std_logic_1164.ads
index d4e396c3e..9903778f5 100644
--- a/src/synth/synth-ieee-std_logic_1164.ads
+++ b/src/synth/synth-ieee-std_logic_1164.ads
@@ -22,6 +22,13 @@ with Types; use Types;
 with Synth.Objtypes; use Synth.Objtypes;
 
 package Synth.Ieee.Std_Logic_1164 is
+
+   --  For std.standard.  Should a package be created ?
+   type Bit is ('0', '1');
+
+   function Read_Bit (M : Memory_Ptr; Off : Uns32) return Bit;
+   procedure Write_Bit (M : Memory_Ptr; Off : Uns32; Val : Bit);
+
    --  From openieee.
 
    --  Unresolved logic state.
@@ -47,6 +54,8 @@ package Synth.Ieee.Std_Logic_1164 is
    function Read_Bit_To_Std_Logic (M : Memory_Ptr; Off : Uns32)
                                    return Std_Ulogic;
 
+   function To_Bit (S : Std_Ulogic; Xmap : Bit) return Bit;
+
    type Table_1d is array (Std_Ulogic) of Std_Ulogic;
    type Table_2d is array (Std_Ulogic, Std_Ulogic) of Std_Ulogic;
 
diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb
index 61aeaba11..bcaadbb0c 100644
--- a/src/synth/synth-static_oper.adb
+++ b/src/synth/synth-static_oper.adb
@@ -939,6 +939,38 @@ package body Synth.Static_Oper is
                return Res;
             end;
 
+         when Iir_Predefined_Ieee_1164_To_Bit =>
+            declare
+               V : Std_Ulogic;
+               X : Bit;
+               R : Bit;
+            begin
+               V := Read_Std_Logic (Param1.Val.Mem, 0);
+               X := Read_Bit (Param2.Val.Mem, 0);
+               R := To_Bit (V, X);
+               return Create_Memory_U8 (Bit'Pos(R), Res_Typ);
+            end;
+         when Iir_Predefined_Ieee_1164_To_Bitvector =>
+            declare
+               El_Type : constant Type_Acc := Get_Array_Element (Res_Typ);
+               Res     : Memtyp;
+               Bnd     : Type_Acc;
+               S       : Std_Ulogic;
+               X       : Bit;
+               R       : Bit;
+            begin
+               X := Read_Bit (Param2.Val.Mem, 0);
+               Bnd := Create_Vec_Type_By_Length
+                 (Uns32 (Vec_Length (Param1.Typ)), El_Type);
+               Res := Create_Memory (Bnd);
+               for I in 1 .. Uns32 (Vec_Length (Param1.Typ)) loop
+                  S := Read_Std_Logic (Param1.Val.Mem, I - 1);
+                  R := To_Bit (S, X);
+                  Write_Bit (Res.Mem, I - 1, R);
+               end loop;
+               return Res;
+            end;
+
          when Iir_Predefined_Ieee_Math_Real_Log2 =>
             declare
                function Log2 (Arg : Fp64) return Fp64;