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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-30 20:56:15 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-30 20:56:15 +0200 |
| commit | e32547e4d3a58aab91ffdc4d770a0b7f4d417fc9 (patch) | |
| tree | bf3f9fc0f647322e9da03ca2ef13848553870510 /src/synth | |
| parent | 2d7866b6583f2888eb66cd75ca64737d4afa4d74 (diff) | |
| download | ghdl-e32547e4d3a58aab91ffdc4d770a0b7f4d417fc9.tar.gz ghdl-e32547e4d3a58aab91ffdc4d770a0b7f4d417fc9.tar.bz2 ghdl-e32547e4d3a58aab91ffdc4d770a0b7f4d417fc9.zip | |
synth: fixes for indexed names.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-decls.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-expr.adb | 10 |
3 files changed, 13 insertions, 3 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index eb86f0c6d..95d01102a 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -567,7 +567,7 @@ package body Netlists.Disp_Vhdl is Iw : constant Width := Get_Width (Get_Input_Net (Inst, 1)); begin Disp_Template - (" process (\i0, \i1)" & NL & + (" process (\i0, \i1, \i2)" & NL & " begin" & NL & " \o0 <= \i0;" & NL & " \o0 (" & diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 8a22c2fa0..b31e2c1cb 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -211,7 +211,9 @@ package body Synth.Decls is -- constraint in some order that is not defined by the language. Etyp := Get_Value_Type (Syn_Inst, El_Type); - if Is_One_Dimensional_Array_Type (Atype) then + if Etyp.Kind = Type_Bit + and then Is_One_Dimensional_Array_Type (Atype) + then St_El := Get_Index_Type (St_Indexes, 0); return Create_Vector_Type (Synth_Bounds_From_Range (Syn_Inst, St_El), Etyp); diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 10173471f..8f7665ace 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -542,7 +542,15 @@ package body Synth.Expr is declare Bnds : constant Value_Acc := Get_Value (Syn_Inst, Atype); begin - return Bnds.Typ.Vbound; + case Bnds.Typ.Kind is + when Type_Vector => + pragma Assert (Dim = 0); + return Bnds.Typ.Vbound; + when Type_Array => + return Bnds.Typ.Abounds.D (Iir_Index32 (Dim + 1)); + when others => + raise Internal_Error; + end case; end; end if; end Synth_Array_Bounds; |