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authorTristan Gingold <tgingold@free.fr>2023-01-11 20:55:41 +0100
committerTristan Gingold <tgingold@free.fr>2023-01-12 06:44:25 +0100
commitf3eba1ac1ef38f7708154e594ede3f72db78105b (patch)
tree7164e9edc9996a4eca8bf53dba7de372f4df5b77 /src/synth
parent783074260833160bfc3ef8f9203147e752e6269e (diff)
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vhdl: clear associated_type in Sem_Generic_Association_Chain
So that it is cleared after use.
Diffstat (limited to 'src/synth')
-rw-r--r--src/synth/synth-vhdl_insts.adb7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb
index 46f2983a2..3e7e59f6c 100644
--- a/src/synth/synth-vhdl_insts.adb
+++ b/src/synth/synth-vhdl_insts.adb
@@ -1058,6 +1058,7 @@ package body Synth.Vhdl_Insts is
Arch : Node;
Config : Node)
is
+ Generic_Chain : constant Node := Get_Generic_Chain (Ent);
Inst_Obj : Inst_Object;
Inst : Instance;
Enc : Name_Encoding;
@@ -1070,6 +1071,10 @@ package body Synth.Vhdl_Insts is
Enc := Name_Parameters;
end if;
+ -- Interning needs access to the actual types of interface types.
+ Set_Interface_Associated
+ (Generic_Chain, Get_Generic_Map_Aspect_Chain (Stmt));
+
-- Search if corresponding module has already been used.
-- If not create a new module
-- * create a name from the generics and the library
@@ -1083,6 +1088,8 @@ package body Synth.Vhdl_Insts is
pragma Assert (Is_Expr_Pool_Empty);
+ Clear_Interface_Associated (Generic_Chain);
+
-- Do the instantiation.
Inst := New_Instance
(Get_Instance_Module (Syn_Inst),